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RT3050/52 datasheet preliminary revision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 1 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years application ? 802.11 b/g/ n ap/router ? nas ? dual band concurrent router ? inic the rt30 52 soc combines ralinks 802.11n draft compliant 2t2r mac/bbp/rf, a high performance 384mhz mips24kec cpu core , 5 - port integrated 10/100 ethernet switch/phy, an usb otg and a gigabit ethernet mac. with the rt3052, there are very few external components required for 2.4ghz 11n wireless products. the rt30 52 employs ralink 2nd generation 11n technologies for longer range and better throughput. the embedded high performance cpu can process advanced applications effortlessly, such as routing, security and voip. the usb por t can be configured to access external storage for digital home applications. in addition, the r t30 52 has rich hardware interfaces (spi/i2s/i2c/uart/gmac) to enable many possible applications. features ? embedded 2 t2r 2.4g cmos rf ? embedded 802.11n 2t2r mac/bbp w/mld enhancement ? 300mbps phy data rate ? 1x1/1x2/2x2 modes ? 20mhz/40mhz channel w idth ? legacy and high throughout modes ? reverse data grant (rdg) support ? compressed block ack ? up to 256 clients ? multiple bssid (up to 8) ? wep64/128, wpa, wpa2 engines ? qos - wmm, wmm power save ? hardware frame aggregation ? international regula tion - 802.11h tpc ? mips 24kec 384mhz with 32kb i cache/16kb d cache ? support 16/32 - bit sdr sdram (up - to 64m bytes) ? sdram data [31:16] sre pin s shared with gpio ? support boot from 8/16 - bit parallel nor type flash (up - to 16m bytes)) ? support boot from nand type flash (up - to 64 m bytes) ? support boot from rom inic mode ? usb2.0 otg x 1 ? embedded a 7 - port ethernet switch and a 5 port 10 /100mbps phy ? support 5 10/100 utp ports and one rgmii/mii port for rt3052 only ? hardware nat, qos, tcp/udp/ip checksum offloading ? slow speed i/o : gpio, i2c, spi, uart, mdc/mdio, jtag,pcm and i2s ? package and i/o voltage ? 14mm x 14mm tf bga - 289 package ? i/o : 3.3v/2.5v(rgmii), 3.3v i/o order information ralink techno logy, corp. (taiwan) 5 th f. no. 36 , taiyuan st, jhubei city, hsin - chu, taiwan, r.o.c. tel: 886 - 3 - 56 0 - 0 868 fax: 886 - 3 - 56 0 - 0 818 ralink technology, corp. (usa) 20833 stevens creek blvd., suite 200 cupertino, ca95014 tel : (408) 725 - 8070 fax: (408)725 - 8069 http://www.ralinktech.com c omparison t able part number temp range package RT3050f - 10~55 0 c green/ rohs compliant tf bga 289 ball (14mmx14mm) rt3052f - 10~55 0 c green/ rohs compliant tf bga 289 ball (14mmx14mm) RT3050f rt3052f package tfbga tfbga dimension 14mmx14mm 14mmx14mm balls 289 289 cpu 320 mhz 320/384 mhz cache 16k i-cache + 16k d-cache 32k i-cache + 16k d-cache sdram 16 bit (32mb) 16/32 bit (64mb) nor flash 8/16 bit (16mb*2) 8/16 bit (16mb*2) nand flash 8bit (32mb) 8bit (32mb) rgmii no yes usb 2.0 yes yes txrx 1x1 2x2 band 2.4 ghz 2.4 ghz power consumption 1.9w 2.3w device feature free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary revision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 2 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years functional block diagram fig. 1 - 1 rt3052 functional block diagram fig. 1 - 2 rt305 0 functional block diagram mips 24kec (384 mhz) 32k i - cache 16k d - cache clock/timer/reset/pll 802.11n 2t2r mac bbp 802.11n 2t2r 2.4ghz rf 2t3r diversity parallel flash controller sdram controller pcm spi i2s i2c usb 2.0 otg ctrl/phy uart full+lite external interface 40mhz crystal fe router transf ormer 8bit/16ibt nor 8bit nand flash 16bit/32bit sdram uart interface usb 2.0 interface eeprom/control audio interface slic codec gpio/led 0 1 2 3 4 gigabit mac fast ethernet switch gbe router gigabit switch mii rgmii dual - band router rt2880/50 rgmii inic or 8bit/16ibt nor 8bit nand flash 16bits sdram uart interface usb 2.0 interface eeprom/control audio interface slic codec gpio/led rj45 (5) mips 24kec (320 mhz) 16k i - cache 16k d - cache clock/timer/reset/pll 802.11n 1t1r mac bbp 802.11n 1t1r 2.4ghz rf 1t1r diversity parallel flash controller sdram controller 0 1 2 3 4 fast ethernet switch pcm spi i2s i2c usb 2.0 otg ctrl/phy uart full+lite external interface 40mhz crystal transformer free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 3 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years table of content 1. pin description ................................ ................................ ................................ .................. 7 1.1 289 - pins bga package diagram ................................ ................................ .................. 7 1.1.1 289 - pins bga package diagram for RT3050f ................................ ........................... 7 1.1.2 289 - pins bga package diagram for rt3052f ................................ ........................... 8 1.2 pin description ................................ ................................ ................................ .......... 9 1.3 pins sharing scheme ................................ ................................ ................................ 17 1.4 boot strapping signal description ................................ ................................ ............. 21 2. maximum rat ings and operating conditions ................................ ................................ ..... 22 2.1 absolute maximum ratings ................................ ................................ ...................... 22 2.2 thermal information ................................ ................................ ................................ 22 2.3 operating conditions ................................ ................................ ............................... 22 2.4 storage condition ................................ ................................ ................................ .... 22 2.5 dc electrical characteristics ................................ ................................ ..................... 22 2.6 ac electrical characteristics ................................ ................................ ..................... 23 2.6.1 sdram interface ................................ ................................ ................................ . 23 2.6.2 flash/ sram interface ................................ ................................ .......................... 24 2.6.3 rgmii interface ................................ ................................ ................................ ... 25 2.6.4 power on sequence ................................ ................................ ............................ 26 3. function description ................................ ................................ ................................ ........ 27 3.1 overview ................................ ................................ ................................ ................ 27 3.2 memory map summary ................................ ................................ ........................... 29 3.3 mips 24kec processor ................................ ................................ .............................. 31 3.3.1 features ................................ ................................ ................................ ............. 31 3.3.2 block diagram ................................ ................................ ................................ ..... 32 3.4 system control ................................ ................................ ................................ ........ 33 3.4.1 features ................................ ................................ ................................ ............. 33 3.4.2 block diagram ................................ ................................ ................................ ..... 33 3.4.3 register description (base: 0x1000.0000) ................................ ............................ 33 3.5 timer ................................ ................................ ................................ ...................... 38 3.5.1 features ................................ ................................ ................................ ............. 38 3.5.2 block diagram ................................ ................................ ................................ ..... 38 3.5.3 register description (base: 0x1000.0100) ................................ ............................ 38 3.6 interrupt control ler ................................ ................................ ................................ . 42 3.6.1 features ................................ ................................ ................................ ............. 42 3.6.2 block diagram ................................ ................................ ................................ ..... 42 3.6.3 register d escription (base: 0x1000.0200) ................................ ............................. 42 3.7 uart ................................ ................................ ................................ ...................... 46 3.7.1 features ................................ ................................ ................................ ............. 46 3.7.2 loop - back control for communications link fault isolation block diagram ............... 46 3.7.3 register description (base: 0x1000.0500) ................................ ............................. 46 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 4 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.8 uart lite ................................ ................................ ................................ ................ 52 3.8.1 features ................................ ................................ ................................ ............. 52 3.8.2 block diagram ................................ ................................ ................................ ..... 52 3.8 .3 register description (base: 0x1000.0c00) ................................ ............................. 52 3.9 programmable i/o ................................ ................................ ................................ ... 57 3.9.1 features ................................ ................................ ................................ ............. 57 3.9.2 block diagram ................................ ................................ ................................ ..... 57 3.9.3 register description (base: 0x1000.0600) ................................ ............................. 57 3.10 i2c controller ................................ ................................ ................................ .......... 64 3.10.1 features ................................ ................................ ................................ ............ 64 3.10.2 block diagram ................................ ................................ ................................ ... 64 3.10.3 register description (base: 0x1000.0900) ................................ ........................... 64 3.11 spi controller ................................ ................................ ................................ .......... 68 3.11.1 features ................................ ................................ ................................ ............ 68 3.11.2 block diagram ................................ ................................ ................................ ... 68 3.11.3 register description (base: 0x1000.0b00) ................................ ........................... 68 3.12 generic dma controller ................................ ................................ ........................... 71 3.12.1 features ................................ ................................ ................................ ............ 71 3.12.2 block diagram ................................ ................................ ................................ ... 71 3.12.3 register description (base: 0x10000 700) ................................ ............................ 71 3.13 pcm controller ................................ ................................ ................................ ........ 75 3.13.1 features ................................ ................................ ................................ ............ 75 3.13.2 block d iagram ................................ ................................ ................................ ... 75 3.13.3 register description (base: 0x1000.0400) ................................ ........................... 76 3.14 i2s controller ................................ ................................ ................................ .......... 80 3.14.1 features ................................ ................................ ................................ ............ 80 3.14.2 block diagram ................................ ................................ ................................ ... 80 3.14.3 register description (base: 0x1000.0a00) ................................ ........................... 81 3.15 memory controller ................................ ................................ ................................ .. 83 3.15.1 features ................................ ................................ ................................ ............ 83 3.15.2 block diagram ................................ ................................ ................................ ... 83 3.15.3 register description (base: 0x1000.0300) ................................ ........................... 83 3.16 nand flash controller ................................ ................................ ............................. 88 3.16.1 features ................................ ................................ ................................ ............ 88 3.16.2 block diagram ................................ ................................ ................................ ... 88 3.16.3 register description (base: 0x1000.0800) ................................ ........................... 88 3.17 frame engine ................................ ................................ ................................ .......... 91 3.17.1 features ................................ ................................ ................................ ............ 91 3.17.2 block diagram ................................ ................................ ................................ ... 92 3.17.3 register description (base: 0x1010.0000) ................................ ........................... 95 3.18 ethernet switch ................................ ................................ ................................ ..... 111 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 5 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.18.1 feature s ................................ ................................ ................................ .......... 111 3.18.2 block diagram ................................ ................................ ................................ . 112 3.18.3 register description (base: 0x1011.0000) ................................ ......................... 113 3.18.4 mii control register ................................ ................................ .......................... 127 3.19 usb otg controller & phy ................................ ................................ ..................... 130 3.19.1 features ................................ ................................ ................................ .......... 130 3.19.2 block diagram ................................ ................................ ................................ . 130 3.19.3 register description (base: 0x101c.0000) ................................ ......................... 131 3.20 802.1 1n 2t2r mac/bbp ................................ ................................ ......................... 180 3.20.1features ................................ ................................ ................................ .......... 180 3.20.2block diagram ................................ ................................ ................................ .. 180 3 .20.3register description (base: 0x1018.0000) ................................ ......................... 181 4. package physical dimension ................................ ................................ ........................... 233 4.1 tfbga 289b 14140.94mm ................................ ................................ ............ 233 5. revision history ................................ ................................ ................................ ............. 235 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 6 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years table of figures fig. 1 - 1 rt3052 functional block diagram ................................ ................................ ......................... 2 fig. 1 - 2 RT3050 functional block diagram ................................ ................................ ......................... 2 fig. 1 - 3 - 1 rt3052 mii ? mii phy ................................ ................................ ................................ .... 18 fig. 1 - 3 - 2 rt3052 rvmii ? mii mac ................................ ................................ ............................... 19 fig. 1 - 3 - 3 rt3052 rgmii ? rgmii phy ................................ ................................ ........................... 19 fig. 1 - 3 - 4 rt3052 rgmii ? rgmii mac ................................ ................................ .......................... 20 fig. 2 - 6 - 1 sdram interface ................................ ................................ ................................ .............. 23 fig. 2 - 6 - 2 flash/sram interface ................................ ................................ ................................ ...... 24 fig. 2 - 6 - 3 rgmii interface ................................ ................................ ................................ ............... 25 fig. 2 - 6 - 4 power on sequence ................................ ................................ ................................ ........ 26 fig. 3 - 1 - 1 rt3052 blo ck d iagram ................................ ................................ ................................ ...... 27 fig. 3 - 1 - 2 RT3050 block d iagram ................................ ................................ ................................ ...... 27 fig. 3 - 3 - 1 mips 24kec processor d iagram ................................ ................................ ......................... 32 fig. 3 - 5 - 1 timer block diagram ................................ ................................ ................................ ........ 38 fig. 3 - 6 - 1 interrupt controller block diagram ................................ ................................ ................... 42 fig. 3 - 7 - 1 uart b lock diagram ................................ ................................ ................................ ......... 46 fig. 3 - 8 - 1 uart lite block diagram ................................ ................................ ................................ .. 52 fig. 3 - 9 - 1 program i/o block diagram ................................ ................................ .............................. 57 fig. 3 - 10 - 1 i2c controller block diagram ................................ ................................ ........................... 64 fig. 3 - 11 - 1 spi controller block diagram ................................ ................................ ........................... 68 fig. 3 - 12 - 1 generic dma controller block diagram ................................ ................................ ............ 71 fig. 3 - 13 - 1 pcm controller block diagram ................................ ................................ ........................ 75 fig. 3 - 14 - 1 i2s transmitter block diagram ................................ ................................ ........................ 80 fig. 3 - 14 - 2 i2s transmitter ................................ ................................ ................................ .............. 80 fig. 3 - 15 - 1 flash/sram/sdram controller block diagram ................................ ................................ . 83 fig. 3 - 15 - 2 flash/sram/sdram controller r/w waveform ................................ ............................... 85 fig. 3 - 16 - 1 nand flash controller block diagram ................................ ................................ ............. 88 fig. 3 - 17 - 1 frame engine block diagram ................................ ................................ ........................... 92 fig. 3 - 17 - 2 pdma fifo - like ring concept ................................ ................................ ......................... 93 fig. 3 - 17 - 3 pdma tx descriptor format ................................ ................................ ........................... 94 fig. 3 - 17 - 4 pdma rx descriptor format ................................ ................................ ........................... 95 fig. 3 - 18 - 1 ethernet switch block diagram ................................ ................................ ..................... 112 fig. 3 - 19 - 1 1.1 usb otg controller & phy block diagram ................................ ............................... 130 fig. 3 - 20 - 1 802.11n 2t2r mac/bbp block diagram ................................ ................................ ......... 180 fig. 3 - 20 - 2 802.11n 2t2r mac/bbp register map ................................ ................................ ........... 181 fig. 3 - 20 - 3 tx frame information ................................ ................................ ................................ ... 223 fig. 3 - 20 - 4 tx descriptor format ................................ ................................ ................................ ... 224 fig. 3 - 20 - 5 txwi format ................................ ................................ ................................ ................ 224 fig. 3 - 20 - 6 rx descriptor ring ................................ ................................ ................................ ........ 226 fig. 3 - 20 - 7 rx descriptor format ................................ ................................ ................................ ... 226 fig. 3 - 20 - 8 rxwi format ................................ ................................ ................................ ............... 227 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 7 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1. pin description 1.1 289 - pins bga package diagram 1.1.1 289 - pins bga package diagram for RT3050f to p view (left portion) top view (right portion) 1 2 3 4 5 6 7 8 9 a rf0_v12a rf0_2g_outp rf0_2g_inn rf0_2g_inp pll_vc_cap bg_res_12k ldorf_out_v12 rf_bb2_v12a adc_vrefn b nc gnd rf_bb1_v12a vco_vco_v12a pll_div_v12a ldopll_out_v12 ldorf_in_vx rf0_tssi_in adc_v12a c nc rf1_v12a gnd vco_lo_v12a pll_pre_v12a pll_x1 pll_x2 base_trx_ip base_trx_qn d nc rf0_pa_pe rf0_lo_v12a gnd gnd bg_v33a nc base_trx_in base_trx_qp e nc rf_v33a nc gnd gnd gnd gnd gnd gnd f dsr_n txd ant_trn wlan_led_n gnd gnd gnd gnd gnd g cts_n rts_n txd2 ant_trnb gnd gnd gnd gnd gnd h uphy_vdda_v33a uphy_vres dcd_n rxd2 soc_co_v12d gnd gnd gnd gnd j uphy_padp uphy_padm rxd dtr_n soc_io_v33d gnd gnd gnd gnd k nc nc uphy_vbus rin gnd gnd gnd gnd gnd l nc nc uphy_id uphy_vddl_v12d soc_co_v12d gnd gnd gnd gnd m nc nc nc soc_co_v12d nc rgmii_io_v33d rgmii_io_v33d gnd gnd n nc nc nc rgmii_io_v33d rgmii_io_v33d ephy_v33a ephy_v33a ephy_v33a ephy_v33a p nc nc nc ephy_ref_res ephy_led3_n ephy_led4_n ephy_led0_n ephy_v33a ephy_v33a r ephy_rxn_p0 ephy_rxp_p0 ephy_txp_p1 ephy_txn_p1 ephy_txp_p3 ephy_txn_p3 ephy_led1_n ephy_led2_n spi_din t ephy_txn_p0 ephy_rxp_p1 ephy_rxn_p2 ephy_txn_p2 ephy_rxp_p3 ephy_rxn_p4 ephy_txn_p4 porst_n spi_clk u ephy_txp_p0 ephy_rxn_p1 ephy_rxp_p2 ephy_txp_p2 ephy_rxn_p3 ephy_rxp_p4 ephy_txp_p4 spi_dout spi_en 10 11 12 13 14 15 16 17 adc_vrefp adc_vref025p adc_vref ldodig_out_v12 sram_cs_n ma20 md1 md6 a adc_v12d adc_vref025n nc oe_n flash_cs_n md0 md5 md4 b rf0_lna_pe ldoadc_in_vx ldodig_in_vx we_n ma21 md3 md8 md9 c gnd ldoadc_out_v12 ldo_v33a ma22 soc_co_v12d md2 md10 md13 d gnd gnd gnd soc_io_v33d soc_co_v12d md7 md14 md15 e gnd gnd gnd gnd soc_co_v12d md11 ma3 ma2 f gnd gnd gnd gnd soc_co_v12d md12 ma1 bpll_vdd_v12d g gnd gnd gnd gnd soc_io_v33d ma4 ma0 bpll_poc_v33d h gnd gnd gnd gnd soc_io_v33d bpll_dvdd_v12d bpll_dvdda_v12d bpll_avdd_v12a j gnd gnd gnd gnd soc_io_v33d ma5 ma7 ma6 k gnd gnd gnd gnd soc_io_v33d soc_co_v12d ma9 ma8 l gnd gnd gnd soc_io_v33d soc_io_v33d ma15 ma11 ma10 m soc_io_v33d soc_io_v33d soc_io_v33d soc_io_v33d nc ma19 ma13 ma14 n soc_co_v12d soc_co_v12d nc nc nc nc ma18 ma12 p i2c_sclk jtag_tdo nc nc nc nc sdram_clk ma17 r i2c_sd jtag_tdi jtag_trst_n nc nc nc sdram_ras_n ma16 t gpio0 jtag_tms jtag_tclk nc nc nc nc sdram_cs_n u free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 8 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1.1.2 289 - pins bga package diagram for rt3052f top view (left portion) top view (right portion) 1 2 3 4 5 6 7 8 9 a rf0_v12a rf0_2g_outp rf0_2g_inn rf0_2g_inp pll_vc_cap bg_res_12k ldorf_out_v12 rf_bb2_v12a adc_vrefn b rf1_2g_inp gnd rf_bb1_v12a vco_vco_v12a pll_div_v12a ldopll_out_v12 ldorf_in_vx rf0_tssi_in adc_v12a c rf1_2g_inn rf1_v12a gnd vco_lo_v12a pll_pre_v12a pll_x1 pll_x2 base_trx_ip base_trx_qn d rf1_2g_outp rf0_pa_pe rf0_lo_v12a gnd gnd bg_v33a rf1_tssi_in base_trx_in base_trx_qp e rf1_pa_pe rf_v33a rf1_lo_v12a gnd gnd gnd gnd gnd gnd f dsr_n txd ant_trn wlan_led_n gnd gnd gnd gnd gnd g cts_n rts_n txd2 ant_trnb gnd gnd gnd gnd gnd h uphy_vdda_v33a uphy_vres dcd_n rxd2 soc_co_v12d gnd gnd gnd gnd j uphy_padp uphy_padm rxd dtr_n soc_io_v33d gnd gnd gnd gnd k ge0_rxdv ge0_rxclk uphy_vbus rin gnd gnd gnd gnd gnd l ge0_rxd3 ge0_rxd0 uphy_id uphy_vddl_v12d soc_co_v12d gnd gnd gnd gnd m ge0_txclk ge0_rxd1 ge0_rxd2 soc_co_v12d mdc rgmii_io_v33d rgmii_io_v33d gnd gnd n ge0_txen ge0_txd0 mdio rgmii_io_v33d rgmii_io_v33d ephy_v33a ephy_v33a ephy_v33a ephy_v33a p ge0_txd1 ge0_txd2 ge0_txd3 ephy_ref_res ephy_led3_n ephy_led4_n ephy_led0_n ephy_v33a ephy_v33a r ephy_rxn_p0 ephy_rxp_p0 ephy_txp_p1 ephy_txn_p1 ephy_txp_p3 ephy_txn_p3 ephy_led1_n ephy_led2_n spi_din t ephy_txn_p0 ephy_rxp_p1 ephy_rxn_p2 ephy_txn_p2 ephy_rxp_p3 ephy_rxn_p4 ephy_txn_p4 porst_n spi_clk u ephy_txp_p0 ephy_rxn_p1 ephy_rxp_p2 ephy_txp_p2 ephy_rxn_p3 ephy_rxp_p4 ephy_txp_p4 spi_dout spi_en 10 11 12 13 14 15 16 17 adc_vrefp adc_vref025p adc_vref ldodig_out_v12 sram_cs_n ma20 md1 md6 a adc_v12d adc_vref025n rf1_lna_pe oe_n flash_cs_n md0 md5 md4 b rf0_lna_pe ldoadc_in_vx ldodig_in_vx we_n ma21 md3 md8 md9 c gnd ldoadc_out_v12 ldo_v33a ma22 soc_co_v12d md2 md10 md13 d gnd gnd gnd soc_io_v33d soc_co_v12d md7 md14 md15 e gnd gnd gnd gnd soc_co_v12d md11 ma3 ma2 f gnd gnd gnd gnd soc_co_v12d md12 ma1 bpll_vdd_v12d g gnd gnd gnd gnd soc_io_v33d ma4 ma0 bpll_poc_v33d h gnd gnd gnd gnd soc_io_v33d bpll_dvdd_v12d bpll_dvdda_v12d bpll_avdd_v12a j gnd gnd gnd gnd soc_io_v33d ma5 ma7 ma6 k gnd gnd gnd gnd soc_io_v33d soc_co_v12d ma9 ma8 l gnd gnd gnd soc_io_v33d soc_io_v33d ma15 ma11 ma10 m soc_io_v33d soc_io_v33d soc_io_v33d soc_io_v33d md26 ma19 ma13 ma14 n soc_co_v12d soc_co_v12d md31 md27 md21 md18 ma18 ma12 p i2c_sclk jtag_tdo md25 md30 md22 md19 sdram_clk ma17 r i2c_sd jtag_tdi jtag_trst_n md28 md20 md16 sdram_ras_n ma16 t gpio0 jtag_tms jtag_tclk md29 md24 md23 md17 sdram_cs_n u free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 9 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1.2 pin description pin name i/o/ipu/ipd description jtag interfaces : 5 pins t12 jtag_trst_n i, ipu jtag trst. u12 jtag_tclk i jtag tclk. u11 jtag_tms i jtag tms. t11 jtag_tdi i jtag tdi. r11 jtag_tdo o jtag tdo. uart lite interface : 2 pins h4 rxd2 i, ipd uart lite rxd. g3 txd2 o uart lite txd. uart full interface : 8 pins j3 rxd i, ipd uart rxd. k4 rin i uart rin. g1 cts_n i uart cts_n. f1 dsr_n i uart dsr_n. h3 dcd_n i uart dcd_n. f2 txd o uart txd. j4 dtr_n o uart dt r. g2 rts_n o uart rts. spi interface : 4 pins r9 spi_din i spi din. u8 spi_dout o spi dout. t9 spi_clk o spi clock. u9 spi_en o spi data enable. i2c interface : 2 pins r10 i2c_sclk o, ipu i2c clock. t10 i2c_sd i/o, ipu i2c data. gpio interfa ce : 1 pin u10 gpio0 i/o when nand - flash is applied, this pin should be used as the busy/ready pin. otherwise, it is dedicated as the gpio0 pin misc signals : 4 pins t8 porst_n i, ipu power on reset f4 wlan_led_n o wlan activity led f3 ant_trn o posit ive signal for antenna t/r switch g4 ant_trnb o negative signal for antenna t/r switch 5 - port phy : 26 pins p4 ephy_ref_res i/o connect to an ex ternal resistor to provide accurate bias current r1 ephy_rxn_p0 i 10/100 phy port #0 rxn r2 ephy _rxp_p0 i 10/100 phy port #0 rxp t1 ephy _txn_p0 o 10/100 phy port #0 txn u1 ephy _txp_p0 o 10/100 phy port #0 txp u2 ephy _rxn_p1 i 10/100 phy port #1 rxn t2 ephy _rxp_p1 i 10/100 phy port #1 rxp r4 ephy _txn_p1 o 10/100 phy port #1 txn r3 ephy _txp_p1 o 10/ 100 phy port #1 txp t3 ephy _rxn_p2 i 10/100 phy port #2 rxn u3 ephy _rxp_p2 i 10/100 phy port #2 rxp t4 ephy _txn_p2 o 10/100 phy port #2 txn free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 10 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description u4 ephy _txp_p2 o 10/100 phy port #2 txp u5 ephy _rxn_p3 i 10/100 phy port #3 rxn t5 ephy _rxp_p3 i 10/100 phy port #3 rxp r6 ephy _txn_p3 o 10/100 phy port #3 txn r5 ephy _txp_p3 o 10/100 phy port #3 txp t6 ephy _rxn_p4 i 10/100 phy port #4 rxn u6 ephy _rxp_p4 i 10/100 phy port #4 rxp t7 ephy _txn_p4 o 10/100 phy port #4 txn u7 ephy _txp_p4 o 10/100 phy port #4 txp p7 ephy _led0 _n o 10/100 phy port #0 activity led r7 ephy _led1 _n o 10/100 phy port #1activity led r8 ephy _led2 _n o 10/100 phy port #2 activity led p5 ephy _led3 _n o 10/100 phy port #3 activity led p6 ephy _led4 _n o 10/100 phy port #4 ac tivity led rgmii/mii interface : 12 pins (2.5v or 3.3v) k2 ge 0 _rxclk i/o rgmii/mii rx clock. f or rt3052f nc f or rt 3050f k1 ge 0 _rxdv i rgmii/mii rx data valid. f or rt3052f nc f or rt 3050f l2 ge 0 _rxd0 i rgmii/mii rx data bit #0. f or rt3052f nc f or rt 3050f m2 ge 0 _rxd1 i rgmii/mii rx data bit #1. f or rt3052f nc f or rt 3050f m3 ge 0 _rxd2 i rgmii/mii rx data bit #2. f or rt3052f nc f or rt 3050f l1 ge 0 _rxd3 i rgmii/mii rx data bit #3. f or rt3052f nc f or rt 3050f m1 ge 0 _txclk i/o rgmii/mii t x clock. f or rt3052f nc f or rt 3050f n1 ge 0 _txen o rgmii/mii tx data enable. f or rt3052f nc f or rt 3050f n2 ge 0 _txd0 o rgmii/mii tx data bit #0. f or rt3052f nc f or rt 3050f p1 ge 0 _txd1 o rgmii/mii tx data bit #1. f or rt3052f nc f or rt 3050f p2 ge 0 _txd2 o rgmii/mii tx data bit #2. f or rt3052f nc f or rt 3050f p3 ge 0 _txd3 o rgmii/mii tx data bit #3. f or rt3052f nc f or rt 3050f phy management interface : 2 pins (2.5v or 3.3v) m5 mdc o phy management clock . f or rt3052f nc f or RT3050f n3 mdio i/o phy management data. f or rt3052f nc f or RT3050f usb otg phy interface : 5 pins h2 uphy_vres i/o connect to an ex ternal 8.2k ohm resistor for band - gap reference circuit k3 uphy_vbus i/o usb otg vbus pin; connect to the vbus pin of the u sb connec tor j2 uphy_padm i/o usb otg data pin data - free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 11 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description j1 uphy_padp i/o usb otg data pin data+ l3 uphy_id i/o usb otg id pin. connect to id pin on the mini - type connec t sdram/flash/sram interface : 62pins p12 md31 i/o sdram/flash/sram data bit #31 for r t3052f nc for RT3050f r13 md30 i/o sdram/flash/sram data bit #30 for rt3052f nc for RT3050f u13 md29 i/o sdram/flash/sram data bit #29 for rt3052f nc for RT3050f t13 md28 i/o sdram/flash/sram data bit #28 for rt3052f nc for RT3050f p13 m d27 i/o sdram/flash/sram data bit #27 for rt3052f nc for RT3050f n14 md26 i/o sdram/flash/sram data bit #26 for rt3052f nc for RT3050f r12 md25 i/o sdram/flash/sram data bit #25 for rt3052f nc for RT3050f u14 md24 i/o sdram/flash/sram data b it #24 for rt3052f nc for RT3050f u15 md23 i/o sdram/flash/sram data bit #23 for rt3052f nc for RT3050f r14 md22 i/o sdram/flash/sram data bit #22 for rt3052f nc for RT3050f p14 md21 i/o sdram/flash/sram data bit #21 for rt3052f nc for rt30 50f t14 md20 i/o sdram/flash/sram data bit #20 for rt3052f nc for RT3050f r15 md19 i/o sdram/flash/sram data bit #19 for rt3052f nc for RT3050f p15 md18 i/o sdram/flash/sram data bit #18 for rt3052f nc for RT3050f u16 md17 i/o sdram/flash/sr am data bit #17 for rt3052f nc for RT3050f t15 md16 i/o sdram/flash/sram data bit #16 for rt3052f nc for RT3050f e17 md15 i/o sdram/flash/sram data bit #15 e16 md14 i/o sdram/flash/sram data bit #14 d17 md13 i/o sdram/flash/sram data bit #13 g 15 md12 i/o sdram/flash/sram data bit #12 f15 md11 i/o sdram/flash/sram data bit #11 d16 md10 i/o sdram/flash/sram data bit #10 c17 md9 i/o sdram/flash/sram data bit #9 c16 md8 i/o sdram/flash/sram data bit #8 e15 md7 i/o sdram/nand or nor flash/sram data bit #7 a17 md6 i/o sdram/nand or nor flash/sram data bit #6 b16 md5 i/o sdram/nand or nor flash/sram data bit #5 b17 md4 i/o sdram/nand or nor flash/sram data bit #4 c15 md3 i/o sdram/nand or nor flash/sram data bit #3 d15 md2 i/o sdram/nand or n or flash/sram data bit #2 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 12 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description a16 md1 i/o sdram/nand or nor flash/sram data bit #1 b15 md0 i/o sdram/nand or nor flash/sram data bit #0 d13 ma22 i/o flash/sram address bit #22 this pin is shared with nand flash cle c14 ma21 i/o flash/sram address bit #21 this pin is shared with nand flash re_n a15 ma20 i/o, ipd flash/sram address bit #20 this pin is shared with nand flash we_n n15 ma19 i/o,ipd flash/sram address bit #19 or sdram dqm bit#3 p16 ma18 i/o, ipd flash/sram address bit #18 or sdram dqm bit#2 r17 ma17 i/o , ipu flash/sram address bit #17 or sdram dqm bit#1 t17 ma16 i/o , ipd flash/sram address bit #16 or sdram dqm bit#0 m15 ma15 i/o , ipu flash/sram address bit #15 or sdram ba bit#1 n17 ma14 i/o , ipu flash/sram address bit #14 or sdram ba bit#0 n16 ma13 i/o , ipd sdram/flash/sram address bit #13 this pin is shared with nand flash ale p17 ma12 i/o , ipd sdram/flash/sram address bit #12 m16 ma11 i/o , ipd sdram/flash/sram address bit #11 m17 ma10 i/o , ipd sdram/flash/sram address bit #10 l16 ma9 i/o , ipd sdram/flash/sram address bit #9 l17 ma8 i/o , ipd sdram/flash/sram address bit #8 k16 ma7 i/o , ipd sdram/flash/sram address bit #7 k17 ma6 i/o , ipd sdram/flash/sram address bit #6 k15 ma5 i/o , ipd sdram/flash/sram address bit #5 h15 ma4 i/o , ipd sdram/flash/sram address bit #4 f16 ma3 i/o , ipd sdram/flash/sram address bit #3 f17 ma2 i/o , ipd sdram/flash/sram address bit #2 g16 ma1 i/o , ipd sdram/flash/sram address bit #1 h16 ma0 i/o , ipd sdram/flash/sram address bit #0 t16 sdram_ras_n o sdram row addr ess select u17 sdram_cs_n o sdram chip select r16 sdram_clk o sdram clock c13 we_n o flash/sram write enable and sdram write enable (sdram_we_n) b13 oe_n o flash/sram write output enable and sdram column address select ( sdram_cas_n) b14 flash_cs_n o flash chip select or nand flash cs_n if boot from nand is selected. a14 sram_cs_n o sram chip select rf interface, related ldo and power pins : 47 pins a4 rf0_2g_inp i 2.4ghz rx0 input (positive) a3 rf0_2g_inn i 2.4ghz rx 0 input (negative) a2 rf0_2g_outp o 2.4ghz tx0 output (positive) b1 rf1_2g_inp i 2.4ghz rx1 input (positive) for rt3052f nc f or RT3050f c1 rf1_2g_inn i 2.4ghz rx1 input (negative) nc f or RT3050f d1 rf1_2g_outp o 2.4ghz tx 1 output (positive) for r t3052f nc f or RT3050f d2 rf0_pa_pe o 0~3.3v control for external pa0 (20ma) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 13 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description e1 rf1_pa_pe o 0~3.3v control for external pa1 (20ma) for rt3052f nc f or RT3050f c10 rf0_lna_pe o external lna0 3.3 v power (50ma) b12 rf1_lna_pe o external lna1 3.3 v powe r (50ma) for rt3052f nc f or RT3050f b8 rf0_tssi_in i tx signal strength monitor input0 (0 ~3.3v) d7 rf1_tssi_in i tx signal strength monitor input1 (0 ~3.3v) for rt3052f nc f or RT3050f b3 rf_bb1_v12a p 1.2v supply for analog baseband a8 rf_bb2_v 12a p 1.2v supply for analog baseband d3 rf0_lo _v12 a p 1.2v supply for lo & if e3 rf1_lo _v12 a p 1.2v supply for lo & if a1 rf0_v12 a p 1.2v supply for rf channel 0 c2 rf1_v12 a p 1.2v supply for rf channel 1 e2 rf_v33a p 3.3v supply for pa enable drive rs (40ma) b4 vco_vco_v12a p 1.2v supply for vco core a5 pll_vc_cap i/o pll external loop filter b10 adc_v12d p 1.2v supply for adc digital logics a12 adc_vref i/o main adc referenc e voltage a11 adc_vref025p i/o auxiliary adc reference voltage (p) b1 1 adc_vref025n i/o auxiliary adc reference voltage (n) b9 adc_v12a p 1.2v supply for adc analog blocks a10 adc_vrefp o auxiliary adc reference voltage (p) a9 adc_vrefn o auxiliary adc reference voltage (n) c9 base_trx_qn i/o baseband q 20mhz debug i/o (negative) d9 base_trx_qp i/o baseband q 20mhz debug i/o (postive) d8 base_trx_in i/o baseband i 20mhz debug i/o (negative) c8 base_trx_ip i/o baseband i 20mhz debug i/o (postive) c12 ldodig_in_vx i ldo 1.5 - 2.0v 600ma input d12 ldo_v33a p 3.3v supply for ldos a13 ldodig_o ut_v12 o ldo 1.2v 600ma output for digital core c11 ldoadc_in_vx i ldo 1.5 - 2v 200ma input for adc d11 ldoadc_o ut_v12 o ldo 1.2v 200ma output for adc b7 ldorf_in_vx i ldo 1.5~2 v 300ma input for rf core and pll a7 ldorf_out_v12 o ld o 1.2v 200ma output for rf core b6 ldopll_o ut_v12 o ldo 1.2v 50ma output for rf pll a6 bg_res_12k i/o external reference resistor (12k ohm) d6 bg_v33a p 3.3v supply for band gap reference c6 pll_x1 i crystal oscillator input c7 pll_x2 o crystal oscill ator output b5 pll_div_v12a p 1.2v supply for pll divider c5 pll_pre_v12a p 1.2v supply for pll prescaler c4 vco_lo_v12a p 1.2v supply for vco output buffer other power pins : 39 pins j15 bpll_dvdd_v12d p 1.2v pll digital power supply j16 bpll_dvdda _v12d p 1.2v pll digital power supply j17 bpll_avdd_v12a p 1.2v pll analog power supply h17 bpll_poc_v33d p 3.3v pll digital power supply free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 14 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description g17 bpll_vdd_v12d p 1.2v pll digital power supply n6 ephy_v33 a p 3.3v 10/100 phy analog power supply n7 ephy_v33 a p 3.3v 10/100 phy analog power supply n8 ephy_v33 a p 3.3v 10/100 phy analog power supply n9 ephy_v33 a p 3.3v 10/100 phy analog power supply p8 ephy_v33 a p 3.3v 10/100 phy analog power supply p9 ephy_v33 a p 3.3v 10/100 phy analog power supply n4 rgmi i_io_v33d p 2.5v/3.3v rgmii i/o power supply n5 rgmii_io_v33d p 2.5v/3.3v rgmii i/o power supply m6 rgmii_io_v33d p 2.5v/3.3v rgmii i/o power supply m7 rgmii_io_v33d p 2.5v/3.3v rgmii i/o power supply h1 uphy_vdda_v33a p 3.3v usb phy analog power suppl y l4 uphy_vddl_v12d p 1.2v usb phy digital power supply j5 soc_io_v33d p 3.3v digital i/o power supply m4 soc_co_v12d p 1.2v digital core power supply h5 soc_co_v12d p 1.2v digital core power supply l5 soc_co_v12d p 1.2v digital core power supply p10 soc_co_v12d p 1.2v digital core power supply p11 soc_co_v12d p 1.2v digital core power supply d14 soc_co_v12d p 1.2v digital core power supply e14 soc_co_v12d p 1.2v digital core power supply f14 soc_co_v12d p 1.2v digital core power supply g14 soc_c o_v12d p 1.2v digital core power supply l15 soc_co_v12d p 1.2v digital core power supply e13 soc_io_v33d p 3.3v digital i/o power supply h14 soc_io_v33d p 3.3v digital i/o power supply j14 soc_io_v33d p 3.3v digital i/o power supply k14 soc_io_v33d p 3.3v digital i/o power supply l14 soc_io_v33d p 3.3v digital i/o power supply m14 soc_io_v33d p 3.3v digital i/o power supply n10 soc_io_v33d p 3.3v digital i/o power supply n11 soc_io_v33d p 3.3v digital i/o power supply n12 soc_io_v33d p 3.3v digita l i/o power supply n13 soc_io_v33d p 3.3v digital i/o power supply m13 soc_io_v33d p 3.3v digital i/o power supply ground pins : 70 pins b2 gnd p ground pin c3 gnd p ground pin d4 gnd p ground pin d5 gnd p ground pin d10 gnd p ground pin e4 gnd p ground pin e5 gnd p ground pin e6 gnd p ground pin e7 gnd p ground pin e8 gnd p ground pin e9 gnd p ground pin e10 gnd p ground pin e11 gnd p ground pin free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 15 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description e12 gnd p ground pin f5 gnd p ground pin f6 gnd p ground pin f7 gnd p ground pin f8 gnd p g round pin f9 gnd p ground pin f10 gnd p ground pin f11 gnd p ground pin f12 gnd p ground pin f13 gnd p ground pin g5 gnd p ground pin g6 gnd p ground pin g7 gnd p ground pin g8 gnd p ground pin g9 gnd p ground pin g10 gnd p ground pin g11 gnd p ground pin g12 gnd p ground pin g13 gnd p ground pin h6 gnd p ground pin h7 gnd p ground pin h8 gnd p ground pin h9 gnd p ground pin h10 gnd p ground pin h11 gnd p ground pin h12 gnd p ground pin h13 gnd p ground pin j6 gnd p ground pin j7 gnd p ground pin j8 gnd p ground pin j9 gnd p ground pin j10 gnd p ground pin j11 gnd p ground pin j12 gnd p ground pin j13 gnd p ground pin k5 gnd p ground pin k6 gnd p ground pin k7 gnd p ground pin k8 gnd p ground pin k9 gnd p ground pin k10 gn d p ground pin k11 gnd p ground pin k12 gnd p ground pin k13 gnd p ground pin l6 gnd p ground pin l7 gnd p ground pin l8 gnd p ground pin l9 gnd p ground pin l10 gnd p ground pin free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 16 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pin name i/o/ipu/ipd description l11 gnd p ground pin l12 gnd p ground pin l13 gnd p ground pin m8 gnd p ground pin m9 gnd p ground pin m10 gnd p ground pin m11 gnd p ground pin m12 gnd p ground pin total: 289 pins *note: ipd means internal pull - down; ipu means internal pull - up; p means power. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 17 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1.3 pins sharing scheme some pins are shared with gpio to provide maximum flexibility for system designers. the RT3050/52 provides up to 52 (rt3052)/22(RT3050) gpio pins. users can configure syscfg and gpiomode registers in the system control block to specify the pin function. un less it specified explicitly, all the gpio pins are in input mode after res e t. rgmii_gpio_mode description pin name rgmii_gpio_mode=0 rgmii_gpio_mode=1 ge 0 _rxclk ge 0 _rxclk gpio51 ge 0 _rxdv ge 0 _rxdv gpio50 ge 0 _rxd0 ge 0 _rxd0 gpio49 ge 0 _rxd1 ge 0 _rxd1 gpio4 8 ge 0 _rxd2 ge 0 _rxd2 gpio47 ge 0 _rxd3 ge 0 _rxd3 gpio46 ge 0 _txclk ge 0 _txclk gpio45 ge 0 _txen ge 0 _txen gpio44 ge 0 _txd0 ge 0 _txd0 gpio43 ge 0 _txd1 ge 0 _txd1 gpio42 ge 0 _txd2 ge 0 _txd2 gpio41 ge 0 _txd3 ge 0 _txd3 gpio40 sdram_gpio_mode description pin name sdram_ gpio_mode=0 sdram_gpio_mode=1 {md31:md16} {md31:md16} gpio39~gpio24 mdio_gpio_mode description pin name mdio_gpio_mode=0 mdio_gpio_mode=1 mdc mdc gpio23 mdio mdio gpio22 jtag_gpio_mode description pin name jtag_gpio_mode=0 jtag_gpio_mode=1 jtag_trst_ n jtag_trst_n gpio21 jtag_tclk jtag_tclk gpio20 jtag_tms jtag_tms gpio19 jtag_tdi jtag_tdi gpio18 jtag_tdo jtag_tdo gpio17 uartl_gpio_mode description pin name uartl_gpio_mode=0 uartl_gpio_mode=1 rxd2 rxd2 gpio16 txd2 txd2 gpio15 uartf_share_mode description pin name 3b000 3b001 3b010 3b011 3b100 3b101 3b110 3b111 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 18 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years spi_gpio_mode description pin name spi_gpio_mode=0 spi_gpio_mode=1 spi_din spi_din gpio6 spi_dout spi_dout gpio5 spi_clk spi_clk gpio4 spi_en spi_en gpio3 i2c_gpio_mo de description pin name i2c_gpio_mode=0 i2c_gpio_mode=1 i2c_sclk i2c_sclk gpio2 i2c_sd i2c_sd gpio1 notes : 1. all given gpios are 4ma drive capable. 2. the default direction for gpio pins are input(i.e. tri - state) except the gpio pins (gpio17gpio21) s hared with the jtag interface. the default value for jtag_gpio_mode is 1. 3. mii, rvmii and rgmii interfacing scenarios: a. rt3052 supports mii/rvmii (reversed mii) for 10/100mbps mode and rgmii for 10/100/1000mbps mode. the operation mode is deter mined by boo t strapping settings (please refer to the ge 0 _mode in the nex t session). i. for example, when ge 0 _mode is set to 2b10, reserved mii mode is configured during the boot strapping. in this mode, txclk becomes an output and txd [3:0]/txctl become inputs; rxclk b ecomes an output and rxd [3:0]/rxctl become outputs. please refer to the following application scenarios for better understanding. fig. 1 - 3 - 1 rt3052 mii ? mii phy r t 3 0 5 2 m i i t x c l k r x c l k t x c t l / t x e n t x d [ 3 : 0 ] r x c t l / r x d v r x d [ 3 : 0 ] m d c m d i o m i i p h y m i i g e 0 _ t x c l k g e 0 _ r x c l k g e 0 _ t x c t l g e 0 _ t x d [ 3 : 0 ] g e 0 _ r x c t l g e 0 _ r x d [ 3 : 0 ] m d c m d i o free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 19 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years fig. 1 - 3 - 2 rt3052 rv mii ? m ii mac fig. 1 - 3 - 3 rt3052 rg mii ? rgmii phy g e 0 _ t x c l k g e 0 _ r x c l k g e 0 _ t x c t l g e 0 _ t x d [ 3 : 0 ] g e 0 _ r x c t l g e 0 _ r x d [ 3 : 0 ] m d c m d i o r t 3 0 5 2 r v m i i t x c l k r x c l k t x c t l / t x e n t x d [ 3 : 0 ] r x c t l / r x d v r x d [ 3 : 0 ] m d c m d i o m i i m a c r v m i i r t 3 0 5 2 r g m i i t x c l k r x c l k t x c t l / t x e n t x d [ 3 : 0 ] r x c t l / r x d v r x d [ 3 : 0 ] m d c m d i o r g m i i p h y r g m i i g e 0 _ t x c l k g e 0 _ r x c l k g e 0 _ t x c t l g e 0 _ t x d [ 3 : 0 ] g e 0 _ r x c t l g e 0 _ r x d [ 3 : 0 ] m d c m d i o free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 20 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years fig. 1 - 3 - 4 rt3052 rg mii ? rgmii mac r t 3 0 5 2 r g m i i t x c l k r x c l k t x c t l / t x e n t x d [ 3 : 0 ] r x c t l / r x d v r x d [ 3 : 0 ] r g m i i m a c r g m i i g e 0 _ t x c l k g e 0 _ r x c l k g e 0 _ t x c t l g e 0 _ t x d [ 3 : 0 ] g e 0 _ r x c t l g e 0 _ r x d [ 3 : 0 ] m d c m d i o m d c m d i o free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 21 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1.4 boot strapping signal description pin name boot strapping signal name description ma7..ma0 test_code[7:0] a vec tor to set chip operation/testing modes. in normal operation, please use the default value : 8b00000000 {ma9, ma8} boot_fro m 2b00 : boot from external 16 - bit flash (default) 2b01 : boot from external 8 - bit flash 2b10 : bo ot from external nand flash 2b11 : boot from internal rom ma10 cpu_clk_sel 1b0 : low (320mhz) 1b1 : high (384mhz, default) ma12 big_endian 0 : little endian (default) 1 : big endian ma13 bypass_pll 0 : do not bypass pll (default) 1: bypass pll ma14 boot_addr 0 : cpu boots at address 0x1fc00000(default) 1 : cpu boots at address 0x1f000000 {ma17,ma16} ge_mode gigabit port mode 2b00 : rgmii mode (10/100/1000m bps) 2b01 : mii mode (10/100 mbps) 2b10 : reversed mii mode (10/100 mbps) 2b11 : reserve ma20 inic_8mb_sdram 0 : inic sdram size is 2mb (default) 1 : inic sdram size is 8mb ma21 inic_ee_sdram 0 : take inic sdram size from inic_8mb setting (default) 1 : take inic sdram size from eeprom free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 22 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2. maximum ratings and operating condition s 2.1 absolute maximum ratings supply voltage ....... . .. . .3.6 v vcc to vcc decouple. . . . . . C 0.3 to +0.3v input, output or i/o voltag e .. .. ..... . gnd C 0.3 v to vcc+0.3v 2.2 thermal information thermal resistance ? ja ( o c/w) in free air for tfbga ( 1 4 x1 4 mm) package . .. ..32.5c /w thermal resistance ? j c (oc/w) in free air for tfbga (1 4 x1 4 mm) package . .. . .. 6 c /w maximum junction temperature (plastic package) ....... . ........... ... . .. . 125c maximum lead temp erature (soldering 10s) .. .. ................... 300c 2.3 operating conditions temperature range ....... . . . ....... .. ........ - 10 to 55c core supply voltage...... .... . . .. . .. . 1.2v +/ - 5 % i/o supply voltage . ............. . .. ..... 3.3v +/ - 10% 2.4 storage condition the calculated shelf life in sealed bag is 12 months if stored between 0 c an d 40c at less than 90% relative humidity (rh). after the bag is opened, devices that are subjected to solder reflow or other high temperature processes must be handled in the following manner: a) mounted within 168 - hours of factory conditions < 30 c /60% rh b) storage humidity needs to maintained at <10% rh c) backing is necessary if customer expose the component to air over 168 hrs, backing condition: 125c / 8hrs 2.5 dc electrical characteristics parameters sym conditions min typ max unit 3.3v supply v oltage vcc33 3.0 3.3 3.6 v 1.2v supply voltage vcc12 1.14 1.2 1.26 v 3.3v current consumption icc33 217 ma ma 1. 5 v current consumption icc12 656 ma ma 2.0v current consumption ( @transformer center tap ) icc20 514 ma ma free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 23 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2.6 ac electrical characteristics 2.6.1 sdram interface fig. 2 - 6 - 1 sdram interface symbol description min max unit remark t_in_su setup time for input signals (e.g. md*) 1.5 - ns t_in_hd hold time for input signals 1.7 - ns t_o ut_vld sdra m_clk to output signals (ma*, md*, sdram_ras_n,) valid 0.8 5 ns output load : 8pf s d r a m _ c l k s d r a m i n p u t s s d r a m o u t p u t s t _ i n _ s u t _ i n _ h d t _ o u t _ v l d free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 24 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2.6.2 flash/sram interface fig. 2 - 6 - 2 flash/sram interface please refer to the memory controller section for more informat ion about the timing setting on the flash/sram interface. m d c s _ n w e _ n t a d r c s t w a d r t w e t w h o l d t c s a d r m d c s _ n o e _ n t a d r c s t r a d r t o e t r h o l d t c s a d r m a , w d a t a w a d d r m a w a d d r r d a t a f l a s h , a s y n c . s r a m w r i t e t i m i n g f l a s h , a s y n c . s r a m r e a d t i m i n g free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 25 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2.6.3 rgmii interface fig. 2 - 6 - 3 rgmii interface symbol description min max unit remark t_tx_su setup time for output signals (e.g. ge 0 _txd*, ge 0 _txen) 1.2 - ns output load : 5pf t_tx_hd hold time for output signals 1.2 - ns output load : 5pf t_rx_su setup time for input signals (e.g. ge 0 _rxd*, ge 0 _rxdv) 1.0 - ns t_rx_hd hold time for input signals 1.0 - ns g e 0 _ t x c l k g e 0 _ t x d / t x c t l t _ t x _ s u t _ t x _ h d g e 0 _ r x c l k g e 0 _ r x d / r x c t l t _ r x _ s u t _ r x _ h d free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 26 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2.6.4 power on sequence fig. 2 - 6 - 4 power on sequence symbol description min max unit remark t_ co _ io t ime between core power on to i/o power on 0 - ms t_io_porst_n time between i/o power on to porst_n de - assertion 10 - ms l d o x x x _ i n _ v x s o c _ i o _ v 3 3 d p o r s t _ n t _ c o _ i o t _ i o _ p o r s t _ n free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 27 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3. function d escription 3.1 overview the RT3050/52 soc combines ralinks 802.11n compliant 2t2r mac/bbp/rf, a high performance 384 - mhz mips24kec cpu core, usb o tg controller/phy, and 5(fe)+1(ge) port ethernet switch and a 5 - port 10/100mbps ethernet phy , to enable a mult itude of high performance, cost - effective 802.11n applications. fig. 3 - 1 - 1 rt3052 block d iagram fig. 3 - 1 - 2 RT3050 block d iagram mips 24kec (384 mhz) 32k i - cache 16k d - cache clock/timer/reset/pll 802.11n 2t2r mac bbp 802.11n 2t2r 2.4ghz rf 2t3r diversity parallel flash controller sdram controller pcm spi i2s i2c usb 2.0 otg ctrl/phy uart full+lite external interface 40mhz crystal fe router transf ormer 8bit/16ibt nor 8bit nand flash 16bit/32bit sdram uart interface usb 2.0 interface eeprom/control audio interface slic codec gpio/led 0 1 2 3 4 gigabit mac fast ethernet switch gbe router gigabit switch mii rgmii dual - band router rt2880/50 rgmii inic or 8bit/16ibt nor 8bit nand flash 16bits sdram uart interface usb 2.0 interface eeprom/control audio interface slic codec gpio/led rj45 (5) mips 24kec (320 mhz) 16k i - cache 16k d - cache clock/timer/reset/pll 802.11n 1t1r mac bbp 802.11n 1t1r 2.4ghz rf 1t1r diversity parallel flash controller sdram controller 0 1 2 3 4 fast ethernet switch pcm spi i2s i2c usb 2.0 otg ctrl/phy uart full+lite external interface 40mhz crystal transformer free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 28 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years there are 4 bus masters (mips 24kec, ethernet switch, usb otg, and 802.11n mac/bbp/r f) in the RT3050/52 soc on a high performance, low latency rbus, (ralink bus). in addition, the RT3050/52 soc supports lower speed peripherals such as uart, timer, gpio, i2c, spi, i2s and pcm via a low speed peripheral bus (pbus).the flash/sram/sdram controller is the only bus slave on t he rbus. it includes an advanced memory scheduler to arbitrate the requests from bus masters, enhancing the performance of memory access intensive tasks such as ap/router packet processing. the rt3052 has an embedded 5(fe)+1(ge) port ethernet switch and a 5 - port 10/100. besides the normal l2 switch function, it also embeds ralinks patent pending packet processing engine (ppe) to offload ap/router packet forwarding tasks such as firewall, nat, napt and layer 2 bridging from the mips cpu. it also features a high performance pdma (packet dma) which not only sorts and retrieves packets to and from the sdram but also supports cpu offloading packet functions such as ip/tcp/udp checksum checking/generation, pppoe session id insertion and vlan tag insertion. ral inks packet processing engine technology enables the rt3052 to perform at the level of higher mhz cpus. the RT3050/52 soc embeds ralinks market proven 802.11n 2t2r mac/bbp/rf to provide a 300mbps phy rate on the wireless lan interface. the mac de sign employs a highly efficient dma engine and hardware data processing accelerators, which free the cpu for user applications. the 802.11n 2t2r mac/bbp/rf is designed to support standards based features in the area of security, quality of service and inte rnational regulation resulting in an enhanced end user experience. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 29 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.2 memory map summary start end size description 0000.0000 - 03ff.ffff 64m sdram 0400.0000 - 0fff.ffff <> 1000.0000 - 1000.00ff 256 sysctl 1000.01 00 - 1000.01ff 256 timer 1000.0200 - 1000.02ff 256 intctl 1000.0300 - 1000.03ff 256 mem_ctrl (sdram & flash/sram) 1000.0400 - 1000.04ff 256 pcm 1000.0500 - 1000.05ff 256 uart 1000.0600 - 1000.06ff 256 pio 1000.0700 - 1000.07ff 256 generic dma 1000. 0800 - 1000.08ff 256 nand flash controller 1000.0900 - 1000.09ff 256 i2c 1000.0a00 - 1000.0aff 256 i2s 1000.0b00 - 1000.0bff 256 spi 1000.0c00 - 1000.0cff 256 uartlite 1000.0d00 - 100f.ffff <> 1010.0000 - 1010.ffff 64k frame engine 1011. 0000 - 1011.7fff 32k ethernet switch 1011.8000 1011.9fff 8k rom 1011_a000 1011_ffff <> 1012.0000 - 1012.7fff 32k <> 1012.8000 1012.ffff 32k <> 1013.0000 - 1013.7fff 32k <> 1013.8000 - 1013.ffff 32k <> 1014.0000 - 1017.ffff 256k <> 1018.0000 - 101b.ffff 256k 802.11n mac/bbp 101c.0000 - 101f.ffff 256k usb otg 1020.0000 - 1aff.ffff <> 1b00.0000 - 1bff.ffff 16mb external sram/flash 1c00.0000 - 1eff.ffff <> 1f00.00 00 - 1fff.ffff 16mb(flash) or 4kb(ram) or 8kb(rom) when boot_from = 2b00, up - to 16mb ex ternal 16 - bit flash is mapped. when boot_from = 2b01, up - to 8mb external 8 - bit flash is mapped. when boot_from = 2b10, 4kb internal boot ram is mapped for boot fr om nand application. when boot_from = 2b11, 8kb internal boot rom is mapped for inic application. note : when boot from nand option is enabled (set boot strapping signal: boot_fro m = 2b10), the accessing to the external flash will be remapped to the i nternal 4kb boot sram located in usb otg (0x101e_0000 C 0x101e_3fff). accesses to original flash memory region outside of the 4kb boot sram are invalid in this boot from nand mode. the 4kb sram is also accessible from 0x101e_0000 C 0x101e_3fff memory space . free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 30 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years when the boot from rom option is enabled (set boot strapping signal: boot_from = 2b11), the accessing to the external flash will be remapped to the internal 8kb boot rom located in (0x1011_8000 C 0x1011_9fff). accesses to original flash memory region o utside of the 8kb boot rom is invalid in this boot from rom mode. the 8kb ro m is also accessible from 0x1011_8000 C 0x1011_9fff memory space. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 31 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.3 mips 24kec processor 3.3.1 features ? 8 - stage pipeline ? 32 - bit address paths ? 64 - bit data paths to caches and external interface ? mips32 - compatible instruction set ? multiply - accumulate and multiply - subtract instructions (madd, maddu, msub, msubu) ? targeted multiply instruction (mul) ? zero/one detect instructions (clz, clo) ? wait instruction (wait) ? conditiona l move instructions (movz, movn) ? prefetch instruction (pref) ? mips32 enhanced architecture (release 2) features ? vector ed interrupts and support for external interrupt controller ? programmable exception vector base ? atomic interrupt enable/disable ? gpr shadow r egisters (optionally, one or three additional shadows can be added to minimize latency for interrupt handlers) ? bit field manipulation instructions ? mips32 privileged resource architecture ? mips dsp ase ? fractional data types (q15, q31) ? saturating arithmetic ? s imd instructions operate on 2x16b or 4x8b simultaneously ? 3 additional pairs of accumulator registers ? programmable memory management unit ? 32 dual - entry jtlb with variable page sizes ? 4 - entry itlb ? 8 - entry dtlb ? optional simple fixed mapping translation (fmt) m echanism ? mips16e? code compression ? 16 bit encodings of 32 bit instructions to improve code density ? special pc - relative instructions for efficient loading of addresses and constants ? save & resto re macro instructions for setting up and tearing down stack fra mes within subroutines ? improved support for handling 8 and 16 bit datatypes ? programmable l1 cache sizes ? instruction cache size : 32kb ? data cache size : 16kb ? 4 - way set associative ? up to 8 outstanding load misses ? write - back and write - through support ? 32 - byte cache line size free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 32 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.3.2 block diagram fig. 3 - 3 - 1 mips 24kec processor d iagram free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 33 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.4 system control 3.4.1 features ? provide read - only chip revision registers ? provide a window to access boot - strapping signals ? support memory remapping configurations ? support software re set to each platform building block ? provide registers to deter mine gpio and other peripheral pin muxing schemes ? provide some power - on - reset only test registers for software programmers ? combine miscellaneous registers (such as clock skew control, status reg ister, memo r egisters,etc) 3.4.2 block diagram fig. 3 - 4 - 1 system control block diagram 3.4.3 register description (base: 0x1000.0000) chipid0_3: chip id ascii character 0 - 3 (offset: 0x00) bits type name description initial value 31:24 ro chip_id3 as cii chip name identification character 3 8h30 (0) 8h 33 (3) 8h 54 (t) 8h 52 (r) 8h 20 ( ) h 20 ( ) 8h 32 (2) 8h 35 (5) 2b0 0: dont care eeprom sdram configuration for inic p a l m b u s i n t e r f a c e s y s t e m c t r l r e g i s t e r s b o o t s t r a p p i n g s i g n a l s g p i o p i n m u x i n g s c h e m e m e m o r y r e m a p i n g c p u r b u s w r a p p e r p i n m u x i n g b l o c k p l a t f o r m b l o c k s p e r b l o c k s / w r e s e t c a c h e h i t / m i s s s t r o b e s s o m e m i s c . r e g i s t e r s p p c i , p c m , . . . s y s t e m c o n t r o l b l o c k t o / f r o m m i p s free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 34 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years note: ther e is no special h/w function related to the setting of this bit. that means the firmwar e could use it for other purpose s (as a general purpose bootstrapping). 28 ro inic_8mb_sdram 0: sdram configuration is 2mb for inic 1: sdram configuration is 8mb for inic note : there is no special h/w function related to the setting of this bit . that means the firmware could use it for other purpose s (as a general purpose bootstrapping). bootstrap 27:26 - - reserved 2b0 25:24 ro ge 0 _mode gigabit port mode 2b00 : rgmii mode (10/100/1000m bps) 2b01 : mii mode (10/100 mbps) 2b10 : reversed mi i mode (10/100 mbps) 2b11 : reserved 2 b00 23 - - reserved 1b0 22 ro boot_addr 0 : cpu boots at address 0x1fc00000 1 : cpu boots at address 0x1f000000 1b0 21 ro - bypass_pll 0: not bypass pll 1: bypass pll bootstrap 20 ro big_endian 0: little endian 1: big endian bootstrap 19 - - reserved 1b0 18 ro cpu_clk_sel 0: 320mhz 1: 384 mhz note : system clock is 1/3 of the cpu clk bootstrap 17:16 ro boot_fro m 2b00 : boot from external 16 - bit flash (default) 2b01 : boot from external 8 - bit flash 2b10 : b oot from external nand flash 2b11 : boot from internal rom bootstrap 15:8 r/w test_code[7:0] probe signals selection default value is from bootstrap and can by modify by software bootstrap 7: 4 - - reserved 7b0 3:2 w o sram_cs_mode 2b00: normal sram ch ip select output (active low) 2b01: watch dog reset output (active low for 3 system clocks) 2b10: bt coexistence signal wlan_act output 2b11: reserved. note : these two bits are write only. the read value is always 2b00. 2b00 1 - - reserved 1 b0 0 w o sdram_clk_drv 1b0 : 8ma sdram_clk driving 1b1 : 12ma sdram_clk driving note : this bit is write only. the read value is always 1b0. 1b0 reserved register (offset: 0x14) bits type name description initial value 31:0 - - reserved 32b0 32b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 35 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years teststat2 firmware test status register 2 (offset: 0x1c) bits type name description initial value 31:0 r/w tsetstat2[31:0] firmware test status 2 note: this register is reset only by power on reset. 32b0 32b0 32b0 32b0 2b01 30b0 1b0 1b0 11b0 1b1 2b0 1b0 1b0 : internal 15.625mhz reference clock 1b1 : ex 1b0 6h28 1b0 1b0 : internal 15.625mhz reference clock 1b1 : external reference clock 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 36 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5:0 r/w pcm_clk_div pcm clock divider the source of this divider comes from two places. one is from ref_clk (see 2.2 pin shari ng scheme - uartf share mode) and the other is from internal 15.625mhz reference clock. the pcm clock divider will divide the referenc e clock by (pcm_clk_div+1). the final pcm_clk is obtained from the divided reference clock or external ref_clk clock depend i ng on the pcm_clk_sel setting. 6h3c rstctrl: reset control register (offset: 0x34) bits type name description initial value 31:2 4 - - reserved 8 b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 6b0 1b0 28b0 the rstcpu bit in rstctl. writing a 1 will clear this bit. writing a 0 h 1b0 the rstsys bit in rstctl. writing a 1 will clear this 0 has not effect. 1 b0 writing a 1 will clear this bit. writing a 0 has not effect. 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 37 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gpiomode: gpio purpose select (offset: 0x60) bits type name description initial value 31:10 - - reserved 24b0 1b1 1b1 1b1 1b0 1b1 3b111 1b1 1b1 32b0 32b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 38 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.5 timer 3.5.1 features ? indep endent clock pre - scale for each timer ? independent interrupts for each timer ? two general - purpose timers ? periodic mode ? free - running mode ? time - out mode ? second timer may be used as watchdog timer ? watchdog timer resets system on time - out 3.5.2 block diagram fig. 3 - 5 - 1 timer block diagram 3.5.3 register description (base: 0x1000.0100) tmrstat: timer status register (offset: 0x00) bits type name description initial value 31:6 - - reserved 26b0 writing a 1 to this bit will reset the timer 1 t writing a 0 to this bit has no effect. reading this bit will return a 0. 1b0 writing a 1 to this bit will reset timer 0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 39 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tmr0 load r egister in all other modes. writing a 0 to this bit has no effect. reading this bit will return a 0. 3:2 - - reserved 2b0 1 r/c tmr1int timer 1 interrupt status this bi t is set if timer 1 has expired. the timer 1 interrupt to the processor is set when this bit is 1. writing a 1 to this bit will clear the interrupt. writing a 0 has no effect. 1b0 0 r/c tmr0int timer 0 interrupt status this bit is set if timer 0 ha s expired. the timer 0 interrupt to the processor is set when this bit is 1. writing a 1 to this bit will clear the interrupt. writing a 0 has no effect. 1b0 tmr0 load: timer 0 load value (offset: 0x10) bits type name description initial value 31:1 6 r - - reserved 16b0 16b0 16b0 16hff 16b0 1b0 15b0 1b0 1b0 1b 4b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 40 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years value timer clock frequency 0 1 2 3 . . 14 15 system clock system c lock / 4 system clock / 8 system clock / 16 . system clock / 32768 system clock /65536 note: the pre - scale value should not be changed unless the timer is disabled. tmr1 load: timer 1 load value (offset: 0x20) bits type name description initial value 31:16 - - reserved 16b0 16b0 16b0 6hffff 16b0 1b0 7b0 1b0 1b0 1b0 3b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 41 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years value timer clock frequency 0 system clock 1 system clock / 4 2 s ystem clock / 8 3 system clock / 16 . . . . 14 system clock / 32768 15 system clock / 65536 note: the pre - scale value should not be changed unless the timer is disabled. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 42 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.6 interrupt controller 3.6.1 features ? support a cent ral point for interrupt aggregation for platform related blocks ? separated interrupt enable and disable registers ? support global disable function ? 2 - level interrupt priority selection ? each interrupt source can be directed to irq#0 or irq#1 note : rt3052 supp orts mips 24kecs vector interrupt mechanism. there are 6 hardware interrupts supported by mips 24kec. the interrupt allocation is shown below: mips h/w interrupt pins connect to remark hw_int#5 timer interrupt highest priority hw_int#4 802.11n nic h w_int#3 frame engine hw_int# 2 reserved hw_int#1 other high priority interrupts (irq#1) hw_int#0 other low priority interrupts (irq#0) lowest priority 3.6.2 block diagram fig. 3 - 6 - 1 interrupt controller block diagram 3.6.3 register description (base: 0x1000.0200) irq0stat: interrupt type 0 status after enable mask (offset: 0x00) bits type name description initial value 31:19 - - reserved 13b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 i n t e r r u p t m a s k i n g i n t e r r u p t p r i o r i t y s e l e c t i o n p a l m b u s i n t e r f a c e i n t e r r u p t s ( f r o m p l a t f o r m b l o c k s ) p a l m b u s ( t o / f r o m m i p s ) m i p s 4 k e c i n t e r r u p t c o n t r o l l e r i r q 0 ( l o w - p r i ) i r q 1 ( h i - p r i ) i r q f r o m p c i h o s t / d e v f r a m e e n g i n e ( g i g a b i t n i c ) 8 0 2 . 1 1 n n i c ( e m b e d d e d w l a n m a c / b b p ) i n t # 0 i n t # 1 i n t # 4 i n t # 3 i n t # 5 m i p s t i m e r i n t free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 43 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 7 ro dma dma interrupt status after mask 1b0 6 ro pio pio interrupt status after mask 1b0 5 ro uart uart interrupt status after mask 4 ro pcm pcm interrupt status after mask 1 b0 3 ro ill_acc illegal access interrupt status after mask 1b0 2 ro wdtimer watch dog timer interrupt status after mask 1b0 1 ro timer0 timer 0 interrupt status after mask 1b0 0 ro sysctl system control interrupt status after mask 1b0 these bits a re set if the corresponding interrupt is asserted from the source and with following two conditions ? the interrupt is not masked (bit not set in the intdis register) ? the interrupt type is set to int0 (in the inttype register). note that write to these bit s are ignored and each bit cannot be simultaneously active in both the irq0stat and irq1stat registers. irq1stat: interrupt type 1 status after enable mask (offset: 0x04) bits type name description initial value 31:19 - - reserved 13b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 ? the interrupt is not masked (bit not set in the intdis register) ? the interrupt ty pe is set to int1 (in the inttype register). note that writing to these bits is ignored and each bit cannot be simultaneously active in both the irq0stat and irq1stat registers. inttype: interrupt type (offset: 0x20) bits type name description initial val ue 31:19 - - reserved 13b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 44 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 7 r/w dma dma interrupt status after type 1b0 6 r/w pio pio interrupt status after type 1b0 5 r/w uart uart interrupt status type 1b0 4 r/w pcm pcm interrupt status type 1b0 3 r/w ill_acc illegal access interrupt status type 1b0 2 r/w wdtimer watch dog timer interrupt status type 1b0 1 r/w timer0 timer 0 interrupt status type 1b0 0 r/w sysctl system control interrupt status type 1b0 these bits control whether an interrupt is irq0 or irq1. the interrupt type may be changed at any time; if the interrupt type is changed while the interrupt is active, the interrupt is immediately redirect ed. intraw : raw interrupt status before enable mask (offset: 0x30) bits type name description initial value 31:19 - - reserved 13b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 writing a 1 to this bit allows interrupt masking to be performed based on each interrupts individual enable mask. rns the global status (1 if enabled). 1b0 12b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 45 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5 rw uart uart interrupt enable 1b0 4 rw pcm pcm interrupt enable 1b0 3 rw ill_acc illegal access interrupt enable 1b0 2 rw wdtimer watch dog timer interrupt enable 1b0 1 rw timer0 timer 0 interrupt enable 1b0 0 rw sysctl sys tem control interrupt enable 1b0 writing a 1 to these bits (except the global bit) will enable the mask for the corresponding interrupt. the interrupt is asserted and the bit is set in the irq0stat or irq1stat registers if an interrupt is enabled. writ es of '0' are ignored. reading either the intena or intdis register will return the current mask, where an interrupt is masked (disabled) if the bit is zero, and unmasked (enabled) if the bit is one. intdis: interrupt disable (offset: 0x38) bits type n ame description initial value 31 r/w global global interrupt disable writing a 1 to this bit allows interrupt masking to be performed based on each interrupts individual disable mask. a read returns the global status (1 if disabled). 1b0 12b0 1b0 1b0 1b0 3b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 writing a 1 to these bits (except the global bit) will disable the mask for the corresponding interrupt. the interrupt is asserted and the bit is set in the irq0stat or irq1stat registers if an interrupt is enabled. writing '0' is ignored. reading either the intena or intdis register will ret urn the current mask, where an interrupt is masked (disabled) if the bit is zero, and unmasked (enabled) if the bit is one. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 46 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.7 uart 3.7.1 features ? 16550 - compatible register set, except for divisor latch register ? 5 - 8 data bits ? 1 - 2 stop bits (1 or 2 sto p bits are supported with 5 data bits) ? even, odd, stick or no parity ? all standard baud rates from 40 b/s to 2.5 mb/s ? 16 - byte receive buffer ? 16 - byte transmit buffer ? receive buffer threshold interrupt ? transmit buffer threshold interrupt ? false start bit detec tion in asynchronous mode ? internal diagnostic capabilities ? break simulation 3.7.2 loop - back control for communications link fault isolation block diagram fig. 3 - 7 - 1 uart block diagram 3.7.3 register description (base: 0x1000.0500) rbr: receive buffer register (offs et: 0x00) bits type name description initial value 31:8 - - reserved 24b0 1b0 24b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 47 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years register is empty, the character is moved to the transmitter register, starting transmissi on. ier: interrupt enable register (offset: 0x08) bits type name description initial value 31:4 - - reserved 28b0 1b0 1b0 1: enable transmit buffer empty (thre) interrupt. 0: disable transmit buffer empty (thre) interrupt. 1b0 1b0 24b0 of these bits will be set high to a value of 11. when the fifo of 00. 1b0 2b0 see also interrupt priorities. 3b1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 48 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0 ro intpend interrupt pending 0: an interrupt bit is set and is not masked. 1: no interrupts are pending. 1b0 fcr: fifo control register (offset: 0x10) bits type name description initial value 31:8 - - reserved 24b0 2b0 2b0 1b0 1b0 1b0 1b0 24b0 2b0 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 49 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5 r/w forcepar force parity bit 0: normal functionality. 1: if even parity is sele cted, the (transmitted and checked) parity is forced to '0'; if odd parity is selected, the (transmitted and checked) parity if forced to '1'. 1b0 4 r/w eps even parity select 0: odd parity selected (checksum, including parity is '1'). 1: even parity sel ected (checksum, including parity is '0'). note: this bit is ignored if the pen bit is '0'. 1b0 3 r/w pen parity enable 0: parity is not transmitted or checked. 1: parity is generated (transmit), and checked (receive). 1b0 2 r/w stb stop bit select 0: 1 stop bit is transmitted and received. 1: 1.5 stop bits are transmitted and received if wls is '0'; 2 stop bits are transmitted and received if wls is '1', '2', or '3'. 1b0 1:0: r/w wls[1:0] word length select 0: each character is 5 bits in length 1: ea ch character is 6 bits in length 2: each character is 7 bits in length 3: each character is 8 bits in length 2b0 mcr: modem control register (offset: 0x18) bits type name description initial value 31:5 - - reserved 24b0 wrapped back through 1b0 1b0 1b0 24b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 50 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 7 r/c erinfifo the fifo contains data which had a parity or framing error this bit is set when the fifo contains data that was received with a par ity error, framing error or break condition. 1b0 6 r/c temt transmitter empty this bit is set when the transmitter shift register is empty, it will clear as soon as data is written to the tbr register. 1b0 5 r/c thre transmitter holding register empty this bit is set when the transmitter holding register is empty, it will clear as soon as data is written to the tbr r egister. 1b0 4 r/c bi break interrupt this bit is set if a break is received, that is when the rxd signal is at a low state for more than one character transmission time (from start bit to stop bit). under this condition, a single 'zero' is received. 1b0 3 r/c fe framing error this bit is set if a valid stop bit is not detected. if a framing error occurs, the receiver will attempt to re - s ynchronize by sampling the start bit twice and then takes the data. 1b0 2 r/c pe parity error this bit is set if the received parity is different from the expected value. 1b0 1 r/c oe overrun error this bit is set when a receive overrun occurs. this wi ll happen if a character is received before the previous character has been read by firmware. 1b0 0 r/c dr data ready this bit is set when a character is received, and has been transferred in to the rec eiver buffer register. this bit will reset when all the characters are read from the receiver buffer register. 1b0 msr: modem status register (offset: 0x20) bits type name description initial value 31:8 - - reserved 24b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 51 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years scratc h: scratch register (offset: 0x24) bits type name description initial value 31:8 - - reserved 24b0 8b0 16b0 note: in a standard 16550 implementation, this register is accessible as two 8 - bit halves only. in this implementation, the dl register is accessible as a s ingle 16 - bit entity only. 16h0001 24b0 8b1 24b0 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 52 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.8 uart lite 3.8.1 features ? 2 - pin uart ? 16550 - compatible register set, except for diviso r latch register ? 5 - 8 data bits ? 1 - 2 stop bits (1 or 2 stop bits are supported with 5 data bits) ? even, odd, stick or no parity ? all standard baud rates from 40 b/s to 2.5 mb/s ? 16 - byte receive buffer ? 16 - byte transmit buffer ? receive buffer threshold interrupt ? t ransmit buffer threshold interrupt ? false start bit detection in asynchronous mode ? internal diagnostic capabilities ? break simulation ? loop - back control for communications link fault isolation 3.8.2 block diagram fig. 3 - 8 - 1 uart lite bl ock diagram 3.8.3 register description (base: 0x1000.0c00) rbr: receive buffer register (offset: 0x00) bits type name description initial value 31:8 - - reserved 24b0 8b0 24b0 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 53 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ier : interrupt enable register (offset: 0x08) bits type name description initial value 31:3 - - reserved 29b0 1b0 1b0 1b0 24b0 will be set high to a value of 11. when the a value of 00. 1b0 2b0 see also interrupt priorities. 3b0 1b0 24b0 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 54 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years programmed in the trigger register. the trigger level encoding is as follows: rxtrig trigger level 0 1 2 3 1 4 8 14 note: this register i s not used if the receive fifo is disabled. 5:4 r/w txtrig[1:0] transmitter trigger level the thre interrupt will be asserted if the transmitter buffer depth is less than or equal to the number of characters programmed in the trigger register. the tr igger level encoding is as follows: txtrig trigger level 0 1 2 3 1 4 8 12 2b0 3 r/w dmamode enable dma transfers this bit is writeable and readable, but has no other hardware function. 1b0 2 w txrst transmitter reset writing a '1' to this bit will c lear the transmit fifo and reset the transmitter status. the shift register is not cleared. 1b0 1 w rxrst receive reset writing a '1' to this bit will clear the receive fifo and reset the receiver status. the shift register is not cleared. 1b0 0 r/w fi foena 0: the transmit and receive fifos have the effective depth of one character. 1: the transmit and receive fifos are enabled. note: the fifo status and data are automatically cleared when this bit is changed. 1b0 lcr: line control register (offset: 0 x14) bits type name description initial value 31:8 - - reserved 24b0 2b0 2b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 55 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1: parity is generated (transmit), and checked (receive). 2 r/w stb stop bit select 0: 1 stop bit is transmitted and received. 1: 1.5 stop bits are transmitted and received if wls is '0'; 2 stop bits are transmitted and received if wls is '1', '2', or '3'. 1b0 1:0: r/w wls[1:0] word length select 0: each character is 5 bits in length 1: each character is 6 bits in length 2: each character is 7 bits in length 3: each character is 8 bits in length 2b0 m cr: modem control register (offset: 0x18) bits type name description initial value 31:5 - - reserved 24b0 1b0 7b0 24b0 2b0 tbr r egister. 1b0 tbr r egister. 1b0 1b0 1b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 56 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years dl: clock divider divisor latch (offset: 0x28) bits type name description initial value 31:16 - - reserved 16b0 16h0001 24b0 8b1 clock divider divisor latch high (offset: 0x30) bits type name description initial value 31:8 - - reserved 24b0 8b0 interface control (offset: 0x34) bits type name description initial value 31:1 - - reserved 31b0 set to 0, the output is always driven with the value of the transmit data signal. when set to a 1, 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 57 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.9 programmable i/o 3.9.1 features ? support 5 2 programmable i/os ? parameterized numbers of independent inputs, outputs, and in p uts ? independent polarity controls for each pin ? independently masked edge detect in terrupt on any input transition ? programmable i/o pins are shared pin with sdram, pci, mdio, jtag, uart - lite, uart, spi, pcm and i2c. 3.9.2 block diagram fig. 3 - 9 - 1 program i/o block diagram 3.9.3 register description (base: 0x1000.0600) gpio23_00_ int: programmed i/ o interrupt status (offset: 0x00) bits type name description initial value 31:24 - - reserved 8b0 generate an interrupt. all bits are cleared by writing 1 to either 24b0 8b0 bit will be 1 if a rising edge triggered the interrupt, or 0 if a all bits are cleared by writing 1 to 24b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 58 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pioint register. note: changes to the pio pins can only be detected when the clock is running. gpio23_00_r ena: programmed i/o rising edge interrupt enable (offset: 0x08) bits type name description initial value 31:24 - - reserved 8b0 the data on the corresponding pio pin transitions from a 0 to a 1, i.e. a rising edge. a 1 wi ll allow the interrupt to be set; a 0 24b0 8b0 g pio pin transitions from a 1 to a 0, i.e. a falling edge. a 1 will allow the interrupt to be set; a 0 24b0 8b0 24b0 8b0 to 1; to configure any pin as an input, the corresponding bit should be set to 0. the value driven onto the 24b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 59 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gpio23_00_ pol: programmed i/o pin polarity (offset: 0x28) bits type nam e description initial value 31:24 - - reserved 8b0 corresponding bit should be set to 1; a value of 0 will not modify the pin data. 24b0 8b0 writing a 1 will set the corresponding bit in the piodata register. writing a 0 will have no effect. 24b0 program i/o interrupt (offset: 0x38) bits type name description initial value 31:16 - - reserved 16 b0 generate an interrupt. all bits are cleared by writing 1 to either program i/o edge status (offset: 0x3c) bits type name description initial value 31:16 - - reserved 16 b0 set), the pioedge bit will be 1 if a rising edge triggered the interrupt, or 0 if a falling edge triggered the interrupt. if the 8b0 register. writing a 1 will clear the corresponding bit in the 0 will have no effect. 24b0 8b0 register. writing a 1 will invert the corresponding bit in the egister. writing a 0 will have no effect. 24b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 60 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years will never be set. all bits are cleared by writing 1 to either t his register or the pioint register. note: changes to the pio pins can only be detected when the clock is running. gpio39_24_ rena program i/o rising edge interrupt enable (offset: 0x40) bits type name description initial value 3 1 : 16 - - reserved 1 6 b0 the data on the corresponding pio pin transitions from a 0 to a 1, i.e. a rising edge. a 1 will allow th e interrupt to be set; a 0 b0 program i/o falling edge interrupt enable(offset: 0x44) bits type name description initial value 3 1 : 16 - - reserved 16 b0 the data on the corresponding pio pin transitions from a 1 to a 0, i.e. a falling edge. a 1 will allow the interrupt to be set; a 0 note: edge detection is done after polarity is adjusted according to the piopol register. 16 b0 program i/o data (offset: 0x48 ) bits type name description initial value 31:16 - - reserved 16 b0 b0 program i/o direction (offset: 0x4c) bits type name description initia l value 31:16 - - reserved 16 b0 should be set to 1; to configure any pin as corresponding bit should be set to 0. the value driven onto the b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 61 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gpio39_24_ pol program i/o pin polarity (offset: 0x50) bits type name description initial value 31:16 - - reserved 16 b0 at any pio pin, the corresponding bit should be set to 1; a value of 0 will not modify the pin data. b0 set pio data bit (offse t: 0x54) bits type name description initial value 31:16 - - reserved 16 b0 register. writing a 1 will clear the corresponding bit in the piodata r egister. writing a 0 b0 clear pio data bit [39:24](offset: 0x58) bits type name description initial value 31:16 - - reserved 16 b0 register. writing a 1 will set the corresponding bit in piodata register. writing a 0 will have no effect. b0 toggle pio data bit (offset: 0x5c) bits type name description initial value 31:16 - - reserved 16 b0 register. writing a 1 will invert the corresponding bit in the piodata r egister. writing a 0 will have no effect. b0 program i/o interrupt status (offset: 0x60) bits type name description initial value 31 : 12 - - reserved 20 b cleared by writing 1 to either b0 program i/o edge status (offset: 0x64) bits type name description initial value 23 : 12 - - reserved 20 b0 the pioedge bit will be 1 if a rising edge triggered the interrupt, or 0 if a falling edge triggered the interrupt. if the will never be set. all bits are cleared by writing 1 to either this b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 62 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years note: changes to the pio pins can only be detected when the clock is running. gpio51_40_ rena program i/o rising edge interrupt enable (offset: 0x68) bits type name description initial value 23 : 12 - - reserved 20 b0 the data on the corresponding pio pin transitions from a 0 to a 1, i.e. a rising edge. a 1 will allow the inte rrupt to be set; a 0 b0 program i/o falling edge interrupt enable (offset: 0x6c) bits type name description initial value 23 : 12 - - reserved 20 b0 the data on the corresponding pio pin transitions from a 1 to a 0, i.e. a falling edge. a 1 will allow the interrupt to be set; a 0 note: edge detection is done after polarit y is adjusted according to the piopol register. 12 b0 program i/o data (offset: 0x70 ) bits type name description initial value 23 : 12 - - reserved 20 b0 b0 program i/o direction (offset: 0x74) bits type name description ini tial value 23 : 12 - - reserved 20 b0 should be set to 1; to configure any pin corresponding bit should be set to 0. the value driven onto the b0 program i/o pin polarity(offset: 0x78) bits type name description initial value 23 : 12 - - reserved 20 b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 63 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 11 : 0 r/w piopol [ 11 : 0 ] program i/o pin polarity these bits are used for controlling the polarity of the data driven on or read from the pio pin s. to invert the polarity of the data at any pio pin, the corresponding bit should be set to 1; a value of 0 will not modify the pin data. note: the polarity controls affect both input and output modes. 12 b0 gpio51_40_ set set pio data bit (offset: 0 x7c) bits type name description initial value 23 : 12 - - reserved 20 b0 register. writing a 1 will clear the corresponding bit in the piodata r egister. writing a 0 wil b0 clear pio data bit (offset: 0x80 ) bits type name description initial value 23 : 12 - - reserved 20 b0 register. writing a 1 will set the corresponding bit in the iodata register. writing a 0 will have no effect. b0 toggle pio data bit (offset: 0x84) bits type name description initial value 23 : 12 - - reserved 20 b0 register. writing a 1 will invert the corresponding bit in the piodata r egister. writing a 0 will have no effect. b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 64 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.10 i2c controller 3.10.1 features ? two i2c host controllers ? programmable i2c bus clock rate ? supports the synchronous inter integrated circuits (i2c) serial protocol ? bi - directional data transfer ? programmable address width up to 8 bits ? sequential byte read or write capability ? device address and data address can be transmitted for device, page and address selection ? supports standard mode and fast mode 3.10.2 block diagram fig. 3 - 10 - 1 i2c controller block diagram 3.10.3 register description (base: 0x1000.0900) config: i2c configuration register (offset: 0x00) bits type name description initial value 31:8 - - r eserved 24b0 addr register. program 0 for a 1 bit address, 1 for a 2 3b0 devaddr r egister. this field should be programmed to 6 for 3b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 65 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1 r/w addrdis 0: normal transfers will occur with the address being transmitted, followed by read or write data. 1: the controller will read or write serial data without transferring the address. 1b0 0 r/w devaddis 0: the device address will be trans mitted before the data address. 1: the controller will not transfer the device address. note: if this bit is set, the addrdis bit is ignored, and an address is always transmitted. note: most i2c slave devices require a device address to be transmitted; t his bit should typically be set to 0. 1b0 clkdiv: i2c clock divisor register (offset: 0x04) bits type name description initial value 31:16 - - reserved 16b0 16b0 25b0 devaddis bit in the config register is not set to 1 . 7b0 24b0 addrdis bit is 0. 8b0 24b0 8b0 24b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 66 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 7:0 ro datain[7 :0] i2c data in these bits store the 8 - bits of data received from the ex ternal i2c slave devices during a read transaction. the datardy bit in the status register is set to 1 when data is valid in this register. 8b0 status: i2c status register (offset: 0x18) bits type name description initial value 31:5 - - reserved 27b0 startxfr r egister is written and a transfer is in progress. when this occurs, the write to the startxfr register is ignored. this bit is automatically cleared if firmware writes to the startxfr register when the busy bit cleared. 1b0 startxfr register. 1b0 datain register. this bit is automatically cleared when firmware reads the datai n register. 1b0 dataout register is written to by software, and set to 1 when transmit data is transferred from the datao ut register to the interface shift register. firmware may write to the dataout register when this bit is 1. 1b1 this bit is 1 when the i2c interface is active, and 0 when it is nsfer when this bit is 0, is 1. 1b0 30b0 devaddis is 0, the device address, devaddis is 1 , the address and stop condition written with a 0 for normal i2c bus accesses. addrdis is ignored if this bit is set for a transaction. 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 67 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years device address; if devaddis is 1, this bit is not s hifted out to the device. bytecnt: i2c byte counter register (offset: 0x20) bits type name description initial value 31:6 - - reserved 26b0 6b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 68 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.11 sp i controller 3.11.1 features ? supports spi master operations ? programmable clock polarity ? programmable interface clock rate ? programmable bit ordering ? firmware - controlled spi enable ? programmable payload (address + data) length 3.11.2 block diagram fig. 3 - 11 - 1 spi control ler block diagram 3.11.3 register description (base: 0x1000.0b00) spistat: spi interface status (offset: 0x00) bits type name description initial value 31:2 - - reserved 30b0 note: this bit must be 0 before initiating a transfer. any attempt to start a data transfer will be ignored if this bit is a 1. 1b0 23b0 1b1 1b0 0: the default state of the spiclk is logic 0. 1: the default state of the spiclk is logic 1. 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 69 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 4 r/w txckedge spi clock default state 0: data is transmitted on the rising edge of the spiclk signal. 1: data is transmitted on the falling edge of the spiclk signal. 1b0 3 r/w hizspi tri - state all spi pin 0: spiclk and spiena pin are driven. 1: spiclk and spiena pin are tri - stated. note: this bit overrides all normal functionality. 1b0 2:0 r/w spiclk[2:0] spi clock divide control (the rate in followi ng table should be change in the future) 0: spiclk rate is system clock rate/ 2 1: spiclk rate is system clock rate / 4 2: spiclk rate is system clock rate / 8 3: spiclk rate is system clock rate / 16 4: spiclk rate is system clock rate / 32 5: spiclk rate is system clock rate / 64 6: spiclk rate is system clock rate / 128 7: spiclk is disabled 3b0 spictl: spi interface control (offset: 0x14) bits type name description initial value 31:4 - - reserved 28b0 1b0 when this bit is written with a 1, the contents of the spidata register are transferred to the spi slave device. writing a 0 to 1b0 when this bit is written with a 1, a read from the spi slave is a 0 to this register has no effect. 1b0 1b0 24b0 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 70 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years [0];bit 0 of the command follows the msb of the data. if data is transmitted lsb (least significant bit) first, the command is placed in the lower bits and the data i s placed in the upper bits. read: the command bits are written her e. bit 0 of the command is written to spidata[0]. when the transfer is complete, the data transferred from the slave may be read from the lower bits of this register. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 71 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.12 generic dma controller 3.12.1 features ? support 8 dma channels ? support 8 dma r equests ? programmable hardware channel priority ? programmable dma burst size (1,2,4,8,16 burst transfer) ? support 32 bit wide transaction ? big - endian and little - endian su pport ? support memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral transfers. ? interrupts for each channel. they also can be masked, independently. ? each channel transaction can be masked temporarily by the software, and rel eased by the hardware automatically. 3.12.2 block diagram fig. 3 - 12 - 1 generic dma controller block diagram 3.12.3 register description (base: 0x10000700) gdmasan: gdma channel n source address (offset: 0x00, 0x10, 0x20, 0x3 0, 0x40, 0x50, 0x60, 0x70 ) (n:0~7) bits type name description initial value 31:0 r/w channel source address channel source address: this register contains the source address information 32b0 32b0 dma engine rbus master rbus master arbiter pbus slave ch 0 ch 7 mux interrupt controller rbus interface ( master ) pbus interface ( slave ) rbus interface ( master ) dma interface interrupt interface free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 72 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gdmact0n: gdma channel n control register 0 (offset: 0x08, 0x18, 0x28, 0x38, 0x48, 0x58, 0x68, 0x78) bits type name description initial value 31:16 r/w transfer count these registers contain the number of the data bytes needed to be transfer. 12b0 b0000: dma_req0 b0001: dma_req1 b0010: dma_req2 b0011: dma_req3 b0100: dma_req4 b0101: dma_req5 b0110: dma_req6 b0111: dma_req7 b1000: the source of 4b0 b0000: dma_req0 b0001: dma_req1 b0010: dma_req2 b0011: dma_req3 b0100: dma_req4 b0101: dma_req5 b0110: dma_req6 b0111: dma_req7 b1000: the destination of the transfer is memory 4b0 b0: incremental mode b1: fix mode 1b0 b0: incremental mode b1: fix mode 1b0 b000: 1 transfer b001: 2 transfer b010: 4 transfer b011: 8 transfer b100: 16 transfer 3b0 b1:enable b0:disable 1b0 b1: enable b0: disable 1b0 b1: software mode b0: hardware mode 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 73 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gdmact1n: gdma channel n control register 1 (offset: 0x0c, 0x1c, 0x2c, 0x3c, 0x4c, 0x5c, 0x6c, 0x7c) bits type name description initial value 31:5 -- - reserved -- 4 r/w channel unmasked interrupt enable channel unmasked interrupt enabl e. b1:enable b0:disable b000: channel 0 b001: channel 1 b010: channel 2 b011: channel 3 b100: channel 4 b101: channel 5 b110: channel 6 b111: channel 7 if th e hardware doesnt need to clear any channel mask bit, 4b0 b1: this channel is masked b0: this channel is not masked 1b0 8b0 8b0 8b0 8b0 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 74 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0 r/w arbitration selection select the channel arbitration method. 1b0: channel 0 has the highest priority. channel 1~ channel7 are round - robin. 1b1: channel 0 doesnt have the highest priority. channel0~channel7 are round - rob in. 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 75 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.13 pcm controller 3.13.1 features ? pcm module provides pbus interface for register configuration and data transfer ? two clock sources are reserved for pcm circuit. (from internal clock generator, int_pcm_clk, and from e xternal clock source, ext_pcm_clk) ? pcm module can drive a clock out to external codec (out_clk_freq = int_pcm_clk/n, n = configurable by register, 1<=n<=64). ? 2 channels pcm are available. 4~128 slots are configurable. ? each channel supports a - law(8 - bits)/u - law(8 - bits)/raw - pcm(16 - bits) transfer. ? hardware converter of a - law ? raw - 16 and u - law ? raw - 16 are implemented in design. ? support long/short fsync. ? all signals are driven by rising edge and latched by falling edge. ? last bit of dtx will be tri - stated on falli ng edge. ? begin of slot is configurable by 10 bits registers each channel. ? 32 bytes fifo are available for each channel 3.13.2 block diagram fig. 3 - 13 - 1 pcm controller block diagram two clocks domains are partitioned in this design. p cm converter (ulaw ? raw - 16bit and alaw ? raw - 16bit) are implemented in pcm mxdmx. the thr eshold of fifo is configurable. as the threshold reachs, pcm will (a) trigger the dma interface to notify external dma engine to transfer data. (b) trigger the interru pts to host. the interrupt sources include : - threshold is reached - fifo under run or overrun. - fault is detected at dma interface. pbus itf rfifo (32 bytes) tfifo (32 bytes) rfifo (32 bytes) tfifo (32 bytes) ch1 pcm csr pbus pcm if sys clock domain pcm clock domain pcm module gdma itf ch0 a/ulaw a/ulaw free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 76 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years the a - law and u - law converter is implemented base on itu - g.711 a - law and u - law table. in this design, support a - law/u - law (8 - bits) ? linear pcm(16 - bits) only. a - law ? u - law isnt available now. the data - flow from codec to pcm - controller (rx - flow) is shown as below: pcm - controller latches the data from drx at indicated time slot and then writes it to fifo. if fifo full, the d ata will be lost. as the rx - fifo reach the threshold, two actions may be taken as dma_ena=1 , dma_req will be asserted to r equest a burst transfer. and it will re - check the fifo threshold after dma_end is asserted by gdma. (gdma should be configured before channel is enabled.) assert the interrupt source to notify host. host can check rfifo_avail information then get back the data from fifo. the data - flow from pcm - controller to codec (tx - flow) is shown as below: after gdma is configured, software should con figure and enable the pcm channel. the empty fifo should as dma_ena=1 , dma_req will be triggered to request a burst transfer. and it will re - check the fifo thr eshold after dma_end is asserted by gdma (a burst is completed.). assert the interrupt source to notify host. host will write down the data to tx - fifo. after that, host will recheck tfifo_empty information then write mor e data if available. notice: as dma_ena=1, the burst size of gdma should less than the threshold value. 3.13.3 register description (base: 0x1000.0400) glb_cfg: glb_cfg register (offset: 0x00) bits type name description initial value 31 rw pcm_en pcm enable, 1: enable 0: disable, all fsm and control register of pcm_mxdmx will be clear to default value. 0 30 rw dma_en dma enable 1: enable d ma interface, transfer data with dma 0: disable dma interface, transfer data with software. 0 29:23 - - reserved 0 22:20 rw rff_thres rxfifo threshold, as threshold reach, host/dma will be notified to fill fifo. (unit = word) it should be >2 and <6 as da ta in fifo under the threshold, interrupt & dma will be triggered. 4 19 - - reserved 0 18:16 rw tff_thres txfifo threshold, as threshold reach, host/dma will be notified to fill fifo. (unit = word) it should be >2 and <6. as data in fifo over the thresho ld, interrupt & dma will be triggered. 4 15:10 - - reserved 0 9 rw ch1 - tx_en channel - 1 tx enable 0 8 rw ch0 - tx_en channel - 0 tx enable 0 7:2 - - reserved 0 1 rw ch1 - rx_en channel - 1 rx enable 0 0 rw ch0 - rx_en channel - 0 rx enable 1: enable 0:disable 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 77 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years pcm_cfg: pcm_cfg register (offset: 0x04) bits type name description initial value 31 rw ext_clk_en pcm_clk is generated by ex ternal source. 1: pcm_clk is provided by external 0: pcm_clk is generated by internal clock divider 0 30 rw clkout_en enable the pcm_clk_o ut 1: pcm_clk_out should be free run 0: pcm_clk_out should be pull - low forever. (note: nor mally, the register should be asserted to 1. and it txs dma signals. (write 1 to clear) tx overrun(write 1 to clear) tx underrun(write 1 to clear) d. (write 1 rxs dma signals. (write 1 to clear) rx overrun(write 1 to clear) rx underrun(write 1 to clear) rx lower than the defined threshold. (write 1 txs dma signals. (write 1 to clear) tx overrun(write 1 to clear) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 78 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5 rw ch0t_unr un the fifo of ch0 - tx underrun(write 1 to clear) 0 4 rw ch0t_thres the fifo of ch0 - tx lower than the defined thr eshold. (write 1 to clear) 0 3 rw ch0r_dma_fa ult found any fault of the ch0 - rxs dma signals. (write 1 to clear) 0 2 rw ch0r_ovrun the fifo of ch0 - rx overrun(write 1 to clear) 1 rw ch0r_unrun the fifo of ch0 - rx underrun(write 1 to clear) 0 0 rw ch0r_thres the fifo of ch0 - rx lower than the defined threshold. (write 1 to clear) 0 int_en: int_en register (offset: 0x0c) bits type na me description initial value 31:16 ro - reserved 0 15 rw int15_en enable int_status[15] 0 14 rw int14_en enable int_status[14] 0 13 rw int13_en enable int_status[13] 0 12 rw int12_en enable int_status[12] 0 11 rw int11_en enable int_status[11] 0 10 rw int10_en enable int_status[10] 0 9 rw int9_en enable int_status[9] 0 8 rw int8_en enable int_status[8] 0 7 rw int7_en enable int_status[7] 0 6 rw int6_en enable int_status[6] 0 5 rw int5_en enable int_status[5] 0 4 rw int4_en enable int_status[4] 0 3 rw int3_en enable int_status[3] 0 2 rw int2_en enable int_status[2] 0 1 rw int1_en enable int_status[1] 0 0 rw int0_en enable int_status[0] 0 ff_status: ff_status register (offset: 0x10) bits type name description initial value 31:16 - - reserved 0 15:12 ro ch1rff_avcnt ch1, available fifo space can be read (unit=word) 0 11:8 ro ch1tff_epcnt ch1, available fifo space can be written (unit=word) 8 7:4 ro ch0rff_avcnt ch0, available fifo space can be read (unit=word) 0 3:0 ro ch0tff_epcnt ch0, av ailable fifo space can be written (unit=word) 8 ch0_cfg: ch0 _cfg register (offset: 0x020) bits type name description initial value 31 rw lbk_en loopback enable 1: loopback (asyn - txfifo ? ? ? ? ? ? ? ? free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 79 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 27:10 - - reserved 0 9:0 rw ts_start timeslot starting location 1 ch1_cfg: ch1 _cfg register (offset: 0x24) bits type name description initial value 31 rw lbk_en loopback enable 1: loopback (asyn - txfifo ? ? ? ? ? ? ? ? free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 80 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.14 i2s controller 3.14.1 features ? i2s transmitter, which can be configured as master or slave. ? support 16 - bit data, sample rate 48khz ? support stereo audio data transfer. ? 32 bytes fifo are available for data transmission. ? support gdma access 3.14.2 block diagram the block diagram of i2s transmitter is shown as below fig. 3 - 14 - 1 i2s transmitter block diagram the i2s interface consists of two separate cores, a transmitter and a receiver. both can operate in either master or slave mode. here we will design only the transmitter in master or slave mod e. i2s signal timing: fig. 3 - 14 - 2 i2s transmitter serial data is transmitted in 2s complement with the msb first. the transmitter always sends the msb of the next word one clock period after the ws changes. serial data sent by the transmitter may be synchronized with either the trailing (high - to - low) or the leading (low - to - high) edge of the clock signal. however, the serial data must cpu pbus ctrl gdma parallel - to - serial converter fifo sdram a s y n c i n t e r f a c e r b u s rbus rbus r b u s pbus sd ws sclk i 2 s design csr free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 81 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years be latched into the receiver on the leading edge of the serial clock signal, and so there are s ome restrictions when transmitting data that is synchronized with the leading edge. the word select line indicates the channel being transmitted: ? ws = 0 ; channel 1 (left); ? ws = 1 ; channel 2 (right). ws may change either on a trailing or leading edge of the serial clock, but it doesnt need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the ws line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchron ous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the pr evious word and clear the input for the next word. 3.14.3 register description (base: 0x1000.0a00) i2s_cfg: i2s configuration register (offset: 0x00) bits type name description initial value 31 rw i2s_en i2s enable, 1: enable 0: disable, all control registers of i 2 s will be clear to default value. 0 30 rw dma_en gdma access enable 1: dma enable 0: host enable 0 29:9 - - reserved 8 rw clk_o u t_dis disable i2s clock pad to drive divider clock 1: i2s clock out pin be input pad. 0: i2s clock out pin drive clock - signal to external component. (note: normally, the register should be asserted to 0. and it found any fault of the gdma signals. (write 1 to clear) e fifo is overflow (write 1 to clear) the fifo is underflow (write 1 to clear) the fifo is lower than the defined threshold. (write 1 to clear) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 82 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years int_en: interrupt enable register (offset: 0x08) bits type name descriptio n initial value 31:4 ro - reserved 0 3 rw int3_en enable int_status[3] 0 2 rw int2_en enable int_status[2] 0 1 rw int1_en enable int_status[1] 0 0 rw int0_en enable int_status[0] 0 ff_status: fifo status register (offset: 0xc) bits type name descript ion initial value 31:8 - - reserved 0 7:4 ro avcnt available fifo space can be read (unit=word) 0 3:0 ro epcnt available fifo space can be written (unit=word) 8 fifo_wreg: fifo write register (offset: 0x10) bits type name description initial value 31: 0 w fifo_wdata write data buffer 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 83 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.15 memory controller 3.15.1 features ? support 2 sdram(16b/32b) chip selects ? support 2 flash(sram)(8/16b) chip selects with independent timing parameters ? support 64mb/sdram per chip select ? support 32mb/fl ash(sram) per chip select ? support sdram transaction overlapping by early active and hidden pre - charge ? support user sdram init commands ? support 4 banks per sdram chip select ? sdram burst length : 4 (fixed) ? support wrap - 4 transfer ? support bank - raw - column and r aw - bank - column address mapping 3.15.2 block diagram fig. 3 - 15 - 1 flash/sram/sdram controller block diagram 3.15.2.1 sdram initialization sequence sdrams require an initialization sequence before they are ready for reading and writing. the initi alization sequence is described below. step #1: setting sdram r elated timing in sdram_cfg0 step#2: setting sdram size and refresh time in sdram_cfg1 register with sdram_i nit_start = 1 step#3: read sdram_init_done in sdram_cfg1 register step#4: if sdram_init_done !=1, go to step#3, else sdram initialization sequence finished 3.15.3 register description (base: 0x1000.0300) sdram_cfg0: sd ram configuration 0 (offset: 0x00) bits type name description initial value 31 ro alw ays_o ne use as an identification for rbus controller 1b1 2b00 s d r a m c o n t r o l l e r f l a s h / s r a m c o n t r o l l e r p i n m u x s c h e d u l e r e x t e r n a l i / o p i n s f r o m b u s m a s t e r s free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 84 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 28 r/w twr write recovery time number of system clock cycles C 1. 1b1 27:24 r/w tmr d load mode to any other command delay number of system clock cycles C 1. 4b0001 23:20 r/w trfc auto refresh period number of system clock cycles C 1. 4b1001 19:18 - - reserved 2b00 17:16 r/w tcas read command to data valid delay (cas latency) in num ber of system clock cycles C 1. 2b10 15:12 r/w tras active to precharge command delay in number of system clock cycles C 1. 4b0101 11:10 - - reserved 2b00 9:8 r/w trcd active to read or write delay in number of system clock cycles C 1. 2b10 7:4 r/w trc active to active command period in number of system clock cycles - 1 4b1000 3:2 - - reserved 2b00 1:0 r/w trp precharge command period in number of system clock cycles C 1. 2b10 sdram_cfg1: sdram configuration 1 (offset: 0x04) bits type name desc ription initial value 31 r/w sdram_init_s tart write 1 to perform sdram initialization sequence. can not set it to zero after initialization. 1b0 1b0 1b0 5b0 1b1 2b0 2b01 2b00 2b10 C 16h0600 4b0 2b01 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 85 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3 : reserved note : this value is from boot strapping. 25 - - reserved 1b0 24 r/w csadr0 address hold time from chip select in number of system clock cycles 1b1 23:22 - - reserved 2b0 21:20 r/w twh old0 chip select and data hold time from write enable in number of system clock cycles 2b01 19:18 - - reserved 2b0 17:16 r/w trhold0 chip select hold time from output enable in number of system clock cycles 2b01 15:12 r/w twe0 write enable duration i n number of system clock cycles 4b1111 11:8 r/w toe0 output enable duration in number of system clock cycles 4b1111 7:6 r/w tradr0 read address setup in number of system clock cycles 2b10 5:4 r/w twadr0 write address setup in number of system clock c ycles 2b10 3:2 - - reserved 2b0 1:0 r/w tadrcs0 address setup time prior to chip select in number of system clock cycles 2b01 *ps: flash_width0 (8/16/32 bits) is configured by power on pin capture. note: total of width specified by tadrcs + twadr/tra dr + twe/toe + tw hold/trho ld + tcsadr may not be fewer than 3 clock cycles. fig. 3 - 15 - 2 flash/sram/sdram controller r/w waveform note : total of width specified by tadrcs + twadr/tradr + twe/toe + tw hold/trho ld + tcsadr may not be fewer than 3 clock cycles m d c s _ n w e _ n t a d r c s t w a d r t w e t w h o l d t c s a d r m d c s _ n o e _ n t a d r c s t r a d r t o e t r h o l d t c s a d r m a , w d a t a w a d d r m a w a d d r r d a t a f l a s h , a s y n c . s r a m w r i t e t i m i n g f l a s h , a s y n c . s r a m r e a d t i m i n g free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 86 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years flash_cfg1 : flash bank 1 configuration (offset: 0x0c) bits type name description initial value 31:28 - - reserved 4b0 2b01 1b0 1b1 2b0 2b01 2b0 2b01 4b1111 4b1111 2b10 2b10 2b0 2b01 32b0 1b0 1b0 1b0 1b0 1b0 3b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 87 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 6 - 7 : reserved this value is reset to 0 when ill_acc_addr is written 7:0 ro ill_acc_len indicate the access size of the illegal access. the unit is byte this value is reset to 0 when ill_acc_addr is written. 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 88 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.16 nand flash controller 3.16.1 features ? supports boot from nand flash memory. ? supports read / erase / page program nand flash memory. ? hardware ecc engine. (hardware generating and software correcting) ? the internal 4kbytes boot buffer can be used for another application after booting. ? only supports nand flash memory with 512 - bytes page size and 8 - bits data. ? indirect access for special command. ? configurable write protect register. ? little / bit ending operation. 3.16.2 block diagram fig. 3 - 16 - 1 nand flash controller block diagram 3.16.3 register description (base: 0x1000.0800) ctrl: nand flash control register (offset: 0x0 0 ) bits type name description initial value 31:24 - - reserved 23:16 rw twaitb dummy time pe riod to wait busy signal = clock * (twait+1) 0 15:12 rw thold hold time duration = clock * (thold+1) 0 11:8 rw tperiod period time duration = clock * (tperiod+1) 0 7:4 rw tsetup setup time duration = clock * (tsetup+1) 0 3:2 rw burst_size 0: 1 dw 1: 2 dw 2: 4 dw 3: 8 dw 0 1 rw dbuf_clr clear data buffer 0 0 rw wp write protect 0 boot buffer (4kb) control state machine registers / data buffer ecc encoder / decoder nand flash interface pbus cle ale nce nwe r/nb i/o 0~7 gdma system reg pci arbitor buffer control free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 89 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years trans_cfg: transfer control register (offset: 0x0 4 ) bits type name description initial value 31:30 - - reserved 29:20 rw bnum_data byte number of data to be transferred 528 19 - - reserved 18:16 rw bnum_addr byte number of address note: maximum number is 4 3 15:14 - - reserved 13:12 rw bnum_cmd3 byte number of command 3 0 11:10 rw bnum_cmd2 byte number of command 2 0 9:8 rw bnum_cmd1 byte number of command 1 1 7 rw respb_data respect busy signal after data phase 0 6 rw respb_addr respect busy signal after address phase 0 5 rw respb_cmd3 respect busy signal after command 3 phase 0 4 rw respb_cmd2 respect busy signal after command 2 phase 0 3 rw ecc_ena ecc enab le 0: disable 1: enable note: in read transfer, hw ecc check function will be active. in write transfer, hw ecc generate function will be active. 0 2 rw dma_ena issue a request to generic dma when data read/write. 0: cpu will get/put data from/to data buf fer. 1: gdma will get/put data from/to data buffer. 0 1 rw wr_trans the transfer is read / write. 0: read 1: write 0 0 wc kick_trans kick the a nand flash transfer 0: no transfer 1: kick a transfer note: this bit will auto clear 0 cmd1: command #1 regis ter (offset: 0x0 8 ) bits type name description initial value 31:24 - - reserved 23:16 rw cmd1_byte3 3 rd byte of command 1 0 15:8 rw cmd1_byte2 2 nd byte of command 1 0 7:0 rw cmd1_byte1 1 st byte of command 1 0 cmd2: command #2 register (offset: 0x0 c ) b its type name description initial value 31:24 - - reserved 23:16 rw cmd2_byte3 3 rd byte of command 2 0 15:8 rw cmd2_byte2 2 nd byte of command 2 0 7:0 rw cmd2_byte1 1 st byte of command 2 0 cmd3: command #3 register (offset: 0x 10 ) bits type name descri ption initial value 31:24 - - reserved 23:16 rw cmd3_byte3 3 rd byte of command 3 0 15:8 rw cmd3_byte2 2 nd byte of command 3 0 7:0 rw cmd3_byte1 1 st byte of command 3 0 addr: address register (offset: 0x 14 ) bits type name description initial value 31 :24 rw add_byte4 4 th byte of address free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 90 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 23:16 rw add_byte3 3 rd byte of address 0 15:8 rw add_byte2 2 nd byte of address 0 7:0 rw add_byte1 1 st byte of address 0 data: data register (offset: 0x 18 ) bits type name description initial value 31:0 rw data data for read / write 0 ecc_enc: ecc encode register (offset: 0x 1c ) bits type name description initial value 31:24 - - reserved - 23:16 r enc_byte2 3 rd byte of ecc encode 0 15:8 r enc_byte1 2 nd byte of ecc encode 0 7:0 r enc_byte0 1 st byte of ecc encode 0 status: status register (offset: 0x 20 ) bits type name description initial value 31:17 - - reserved - 16:8 r dec_byte ecc decode fail byte address 0 7 - - reserved 6:4 r dec_bit ecc decode fail bit address 0 3 - - reserved 2 r nd_rb_n nand flash r eady 0: busy 1: ready 1 1 r dec_err ecc decode check status 0: no error 1: correctable error or ecc error 0 0 r busy nand flash controller is in busy. 0: idle 1: busy 0 int_status (offset: 0x 0c , default: 0x00) bits type name description initial value 3 1:8 - - reserved - 7 w1c rx_kick_err rx buffer not empty at host kick 0 6 w1c tx_kick_err tx buffer not empty at host kick 0 5 w1c rx_tras_err rx buffer not empty at transfer done 0 4 w1c tx_tras_err tx buffer not empty at transfer done 0 3 w1c ecc_er r ecc error 0 2 w1c rx_buf_rdy rx buffer read ready 0 1 w1c tx_buf_rdy tx buffer write ready 0 0 w1c nd_done transfer done 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 91 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.17 frame engine 3.17.1 features ? wire - speed (1000mbps) ethernet lan/w an nat/napt routing ? l1 - l7(content aware) policy table ? qos s upport for multimedia traffic ? support per flow/rule accounting/rate limiting ? checksum/vlan/pppoe offload 3.17.1.1 network interfaces ? one 10/100/1000mbps ethernet macs with rgmii/mii interfaces ? one scatter - gather packet dma with rbus master interface ? one special po rt for packet processing engine 3.17.1.2 pse (packet switch engine) features ? four external ports and one special ppe port (for packet bridging/routing) ? efficient page - based buffer management ? qos - aware queue management ? supports 4 output queues/virtual wan/lan port ? w rr/strict priority scheduling ? egress rate limiting/shaping ? non - blocking, wire - speed packet switching ? flow control for no - packet - loss guarantee ? emulated multicast support (can mirror a tx packet to cpu) ? checksum offload, vlan & pppoe header insertion (by cdma) ? auto - padding for sub - 64b packets 3.17.1.3 ppe features ? supports 512 policy rules for acl, accounting and rate limiting. ? the policy rules can base on pre - route/post - route l1 - l7 headers & contents (up - to 16 bytes) ? ddos avoidance by rate limiting ? supports statef ul packet filtering (spi) ? supports ipv4 nat/napt routing ? supports 1/2/4/8/16k ipv4 napt flows ? supports virtual server, port - triggering & port forwarding ? supports any kind of ipv4 nat(napt, twice nat) ? supports 16 pppoe sessions ? supports cone - nat, port - r estr icted nat & symmetric nat ? supports per rule or per flow accounting or rate limiting ? patent - pending flow offloading technology for flexible/high performance packet l3/l4 packet processing ? supports double vlan tagging (q - in - q) ? support vid swapping ? support mu lti - wan load balancing with h/w s/w cooperation ps : all the ppe features mentioned above require software porting to enable. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 92 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.17.1.4 qos related features ? packets can be classified based on l1 - l7 headers/content ? supports 4 tx queues ? supports wrr scheduling for th e two virtual wan and lan ports ? supports egress rate limiting for each network port ? powerful buffer reservation scheme to r eserve packet buffer resources for multi - media traffic. 3.17.1.5 packet dma (pdma) features ? supports 4 tx descriptor rings and one rx descript or ring ? scatter/gather dma ? delayed interrupt ? configurable 4/8/16 32 - bit word burst length 3.17.2 block diagram fig. 3 - 17 - 1 frame engine block diagram p s e ( p a c k e t s w i t c h i n g e n g i n e ) p p e ( p a c k e t p r o c e s s i n g e n g i n e ) g d m a 1 ( l a n ) g d m a 2 ( w a n ) c d m a p d m a e m b e d d e d s w i t h c ( 1 g e + 5 f e p o r t s ) h i g h s p e e d b u s s l o w b u s i n g r e s s p a r s i n g e g r e s s s c h e d u l e / e g r e s s r a t e l i m i t i n g c h e c k s u m o f f l o a d s c a t t e r / g a t h e r i n g d m a n a t / n a p t / s p i / f i r e w a l l r a t e l i m i t i n g / a c c o u n t i n g g e n e r i c p a c k e t s w i t c h f a b r i c c p u p o r t ( p o r t # 0 ) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 93 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.17.2.1 pdma fifo - like ring concept fig. 3 - 17 - 2 pdma fifo - like ring concept 3 1 0 b y t e 0 b y t e 1 b y t e 2 b y t e 3 i c o : i p c h e c k s u m o f f l o a d e n a b l e u d p : u d p c h e c k s u m o f f l o a d e n a b l e t c o : t c p c h e c k s u m o f f l o a d e n a b l e p n : d e s t i n a t i o n p o r t n u m b e r ( 0 : c p u , 1 : g d m a # 1 , 2 : g d m a # 2 , 3 - 5 : r e s e r v e d , 6 : p p e , 7 : d i s c a r d ) q n : d e s t i n a t i o n q u e u e n u m b e r u d f : u s e r d e f i n e f i e l d i n s p : i n s e r t p p p o e h e a d e r s i d x : p p p o e s e s s i o n i n d e x i n s v : i n s e r t v l a n t a g v p r i : v l a n p r i o r i t y t a g t o b e i n s e r t e d v i d x : v l a n i d i n d e x s d p : s e g m e n t d a t a p o i n t e r s d l : s e g m e n t d a t a l e n g t h l s : l a s t s e g m e n t d d o n e : d m a d o n e . i n d i c a t e d m a h a s t r a n s f e r t h e s e g m e n t p o i n t e d b y t h i s t x d e s c r i p t o r b u r s t : w h e n s e t , t h e s c h e d u l e r c a n n o t h a n d - o v e r t o o t h e r t s q u e u e s . s h o u l d g o o n t o t r a n s m i t t h e n e x t p a c k e t s d l 0 [ 1 3 : 0 ] t c o u c o i c o s d p 0 [ 3 0 : 0 ] d d o n e l s 0 q n [ 2 : 0 ] p n [ 2 : 0 ] 0 0 v i d x [ 3 : 0 ] i n s v i n s p s i d x [ 3 : 0 ] t h e d w o r d i s c a l l e d t x i n f o s d p 1 [ 3 0 : 0 ] s d l 1 [ 1 3 : 0 ] l s 1 v p r i [ 2 : 0 ] 5 ' 0 0 0 0 0 0 0 u d f b u r s t free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 94 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.17.2.2 pdma descriptor format fig. 3 - 17 - 3 pdma tx descriptor format rx_done_int(j) rx_dma_busy rx_dma_en tx_crls_idx(i)* ( points to non - released tsd) rx_calc_idx(j) ( points to non - allocated fsd) ( points to non - received dma fsd) ( points to non - received cpu fsd) tx_dtx_idx(i) ( points to non transmitted dma tsd) ( points to non - transmitted cpu tsd) rx_max_cnt t x_max_cnt tx _ pkt # l tx _ pkt # k tx _ pk t # j tx _ pkt # i tx_d ma rx _ pkt # a rx _ pkt # b rx _ pkt # c r x_d ma rx _ pkt # d tx_driver tx_driver ( i = 0 - 3 ) ( j = 0 ) pdma / frame engine software driver tx_ctx_idx(i) rx_crx_idx(j) rx_drx_idx(j) tx_dma_en tx_dma_busy tx_dmne_int(i) pdma_dly_int note 1: tx_crlsidx(i) and rx_crxidx(i) are not in pdma hardware they are resident in cpus local memory note2: txq0: ge mac l ow queue rxq0: for ge mac receive txq1: ge mac high queue free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 95 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years fig. 3 - 17 - 4 pdma rx descriptor format 3.17.3 register description (base: 0x1010.0000) 3.17.3.1 register descriptio n - ge port (base: 0x1010.0000) mdio_access: mdio access (offset: 0x00) bits type name description initial value 31 wsc md_cmd_trg mdio command trigger. this bit is cleared by hardware after command is completed. 1 : read/write operation ongoing 0 : read/w rite operation complete 1b0 1b0 1b0 5b0 3b0 5b0 16b0 reserved (o ffset: 0x04) fe_glo _cfg: frame engine global configuration (offset: 0x08) bits type name description initial value 31:16 r/w ext_vlan extended vlan type 16h8100 running at 133mhz, set this register to 8d132. 8d132 4h8 1b0 3 1 0 b y t e 0 b y t e 1 b y t e 2 b y t e 3 s d p 0 : s e g m e n t d a t a p o i n t e r f o r h d r ( i f h p _ s e p _ e n = 1 ) o r t h e w h o l e p k t ( i f h p _ s e p _ e n = 0 ) s d p 1 : s e g m e n t d a t a p o i n t e r f o r p a y l o a d ( v a l i d w h e n h p _ s e g _ l e n ! = 0 ) s d l 0 : r x w i + p a c k e t h d r l e n g t h ( i f h p _ s e g _ l e n ! = 0 ) , o r r x w i + p k t l e n ( i f h p _ s e g _ l e n ! = 0 ) s d l 1 : = p a y l o a d l e n g t h ( i f h p _ s e g _ l e n ! = 0 ) d d o n e : d m a d o n e . i n d i c a t e d m a h a s r e c e i v e d t h e s e g m e n t s p o i n t e d b y t h i s r x d e s c r i p t o r s d l 0 [ 1 3 : 0 ] s d p 0 [ 3 1 : 0 ] l s 0 t h e d w o r d i s c a l l e d r x i n f o s d p 1 [ 3 1 : 0 ] d d o n e b y t e 3 s d l 1 [ 1 3 : 0 ] 1 0 i p f v l d : i p v 4 & ( h l e n = = 5 ) l 4 f v l d : i p f v l d & n o i p f r a g & ( t c p | u d p ) i p f : i p c h e c k s u m f a i l l 4 f : l 4 c h e c k s u m f a i l a i s : a s s i s t i n f o s e l e c t a i : a s s i s t i n f o p a r _ r l t ( a i s = 0 ) : p a r s e r r e s u l t f o r m p o r t c p u _ r e a s o n ( a i s = 1 ) : c p u r e a s o n f r o m p p e t o c p u f v l d : f o e _ e n t r y v a l i d l 4 f i p f i p f v l d l 4 f v l d f o e _ e n t r y [ 1 3 : 0 ] f v l d a i ( p a r _ r l t [ 7 : 0 ] / c p u _ r e a s o n [ 7 : 0 ) s p [ 2 : 0 ] a i s 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 96 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years fe_rst_glo: frame engine global reset (offset: 0x0c) bits type name description initial value 31:16 rc fc_drop_cnt flow contro l drop packet count. 16b0 15b0 1b0 1b0 1b0 1b0 4b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 4b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 97 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years read to get the raw interrupt status 9 r/w tx_do ne_int1 tx queue#1 packet transmit interrupt write 1 to clear the interrupt. read t o get the raw interrupt status 1b0 8 r/w tx_do ne_int0 tx queue#0 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 1b0 7:3 - - reserved 5b0 2 r/w rx_done_int0 packet receive interrupt. write 1 to clear the interrupt. read to get the raw interrupt status 1b0 1 r/w tx_dly_int delayed version of tx_done_int0 and tx_done_int1. write 1 to clear the interrupt. read to get the raw interrupt status 1b0 0 r/w rx_dly_int delayed version of rx_done_int0. write 1 t o clear the interrupt. read to get the raw interrupt status 1b0 fe_int_enable: frame engine interrupt enable (offset: 0x14) bits type name description initial value 31 r/w cnt_ppe_af ppe counter table almost full 1 : enable the interrupt 0 : disable the interrupt 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 2b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 98 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 16 r/w rx_coherent rx_dma finds data coherent event when checking ddone bit. 1 : enable the interrupt 0 : disable the interrupt 1b0 15:12 - - reserved 4b0 11 r/w tx_do ne_int3 tx queue#3 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 1b0 10 r/w tx_do ne_int2 tx queue#2 packet transmit interrup t 1 : enable the interrupt 0 : disable the interrupt 1b0 9 r/w tx_do ne_int1 tx queue#1 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 1b0 8 r/w tx_do ne_int0 tx queue#0 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 1b0 7:3 - - reserved 5b0 2 r/w rx_done_int0 packet receive s interrupt. 1 : enable the interrupt 0 : disable the interrupt 1b0 1 r/w tx_dly_int delayed version of tx_done_int0 and 1 : enable the interrupt 0 : disable the interru pt 1b0 0 r/w rx_dly_int delayed version of rx_done_int0. 1 : enable the interrupt 0 : disable the interrupt 1b0 mdio_cfg2 reserved (offset: 0x 18) foe_ts_t: time stamp (offset: 0x1c) bits type name description initial value 31:24 r pse_fq_pcnt pse fre e q page count 8hff 8b0 16b0 3.17.3.2 register description C gdma 1 & 2 (base: 0x1010.0020) gdma_fwd_cfg: gdma for warding configuration (offset: 0x00) bits type name description i nitial value 31:24 - - reserved 8b0 1b0 1b1 1b1 1b1 1b0 1b0 1b0 1b1 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 99 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 14:12 r/w gdm_ufrc_p gdma1 & 2 my mac uni - cast frames destination port 3d0 : cpu 3d1 : gdma1 3d2 : gdma2 3d6 : ppe 3d7 : discard others: reserved 3b111 11 - - reserved 1b0 10:8 r/w gdm_bfrc_p gdma1 & 2 broadcast mac address frames destination port 3d0 : cpu 3d1 : gdma1 3d2 : gdma2 3d6 : ppe 3d7 : discard others: reserved 3b111 7 - - reserved 1b0 6:4 r/w gdm_mfrc_p gdma1 & 2 multi - cast mac address frames destination port 3d0 : cpu 3d1 : gdma1 3d2 : gdma2 3d6 : pp e 3d7 : discard others: reserved 3b111 3 - - reserved 1b0 2:0 r/w gdm_ofrc_p gdma1 & 2 other mac address frames destination port 3d0 : cpu 3d1 : gdma1 3d2 : gdma2 3d6 : ppe 3d7 : discard others: reserved 3b111 gdma1_sch_cfg: gdma1 scheduling co nfiguration (offset: 0x04) bits type name description initial value 31:26 - - reserved 7b0 2b00 : wrr 2b01 : strict priority, q3>q2>q1>q0 2b10 : mixed, q3>wrr(q2,q1,q0) 2b11 : reserved 2b00 1b0 q3s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b011 1b0 q2s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : 3b010 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 100 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 6:4 r/w gdm1_w t_q1 q1s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b001 3 - - reserved 1b0 2:0 r/w gdm1_w t_q0 q0s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b0 gdma1_shpr_cfg: gdma1 output shaper configuration (offset: 0x08) bits type name description initial value 31:25 - - reserved 7b0 1b0 8b0 2b0 14b0 32b0 16b0 16b0 3.17.3.3 register description - pse (base: 0x1010.0040) pse_fq_cfg: pse_fq_cfg register (offset:0x00) bits type name description initial value 31:24 r/w fq_max_pcnt maximum free q page count. please reset pse after re - programm ing this register. 8h80 8h50 8h40 8h00 3b0 allows high priority q to share low priority qs rese 1b1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 101 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 27:24 r/w p0_hq_def bit map definition of high priority q. 1 presents high priority q, and 0 presents low priority q. bit 27: q3 priority definition bit 26: q2 priority definition bit 25: q1 priority definition b it 24: q0 priority definition 4b1100 23:16 r/w p0_hq_resv reserved page count for high priority q. 8h10 15:8 r/w p0_lq_resv reserved page count for low priority q. 8h10 7:0 r/w p0_iq_asrt virtual input q fc assertion threshold. 8h10 gdma1_fc_cfg: g dma1_fc_cfg register (offset:0x08) bits type name description initial value 31:29 - - reserved 3b0 allows high priority q to share low priority qs reserved pages. 1b1 gh priority q. 1 presents high priority q, and 0 presents low priority q. 4b1100 8h10 8h10 8h10 3b0 allows high priority q to share low priority qs reserved pages. 1b1 bit map definition of high priority q. 1 presents high priority q, and 0 presents low priority q. 4b1100 8h10 8h10 8h10 8b0 8b0 8b0 8b0 8b0 8b0 8b0 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 102 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gdma2_oq_sta: gdma2 _oq_sta register (offset:0x18) bits type name description init ial value 31:24 ro p2_oq3_pcnt gdma2 output q3 page count. 8b0 8b0 8b0 8b0 8b0 8b0 8b0 8b0 3.17.3.4 register description C gdma2 (base: 0x1010.0060) gdma2_fwd_cfg: reserved (offset: 0x00) gdma2_sch_cfg: gdma2 scheduling configuration (offset: 0x04) bits type name description initial value 31:26 - - reserved 7b0 2b00 : wrr 2b01 : strict priority, q3>q2>q1>q0 2b10 : mixed, q3>wrr(q2,q1,q0) 2b11 : reserved 2b00 1b0 q3s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 3b011 1b0 q2s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b010 1b0 q1s weight 3d0 : weight = 1 3d1 : weig 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b001 1b0 q0s weight 3d0 : weight = 1 3d1 : weight = 2 3d2 : weight = 4 3d3 : weight = 8 3d4 : weight = 16 3b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 103 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gdma2_shpr_cfg: gdma2 output shaper configuration (offset: 0x08) bits type name description initial value 31:25 - - reserved 7b0 1b0 8b0 2b0 14b0 3.17.3.5 register description - cpu port (base:0x1010.0080) cdma_csg_cfg: cdma_csg_cfg register (offset: 0x00) bits type name description initial value 31:16 r/w i ns_vlan_ inserted vlan type 16h8100 13b0 1b0 1b0 1b0 6b0 2b00: wrr 2b01: strict priority, q3>q2>q1>q0 2b10: mixed, q3>wrr(q2,q1,q0) 2b11: reserved 2b00 9b0 q3s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b011 1b0 q2s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b0 1b0 q1s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b001 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 104 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2:0 r/w cdm_w t_q0 q0s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b000 pppoe_sid_0001: pppoe_sid_0001 register (offset: 0x08) bits type name description initial value 31:16 r/w pppoe_sid1 pppoe session id for sid index#1 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 16b0 4b0 12b0 4b0 12b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 105 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years vlan_id_0203: vlan_id_02 03 register (offset: 0x2c) bits type name description initial value 31:28 - - reserved 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b0 4b0 12b 4b0 12b0 4b0 12b0 b0 12b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 106 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.17.3.6 register description - pdma (base: 0x1010.0100) pdma_glo_cfg: pdma_glo _cfg register (offset:0x00) bits type name description initial value 31:30 - - reserved 2b0 14b0 8b0 1b0 1b1 2d2 1b0 1b0 1b0 1b0 15b0 1b0 12b0 1b0 1b0 1b0 1b0 7b0 2b00: wrr 2b01: strict priority, q3>q2>q1>q0 2b10: 2b11: reserved 2b00 1b0 q1s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b011 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 107 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 10:8 r/w pdm_w t_q2 q0s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b010 7 - - reserved 1b0 6:4 r/w pdm_w t_q1 q1s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b001 3 - - reserved 1b0 2 :0 r/w pdm_w t_q0 q0s weight 3d0: weight = 1 3d1: weight = 2 3d2: weight = 4 3d3: weight = 8 3d4: weight = 16 3b000 dly_int_cfg: dly_int_cfg register (offset: 0x0c) bits type name description initial value 31 rw txdly_int_en 1: enable tx delayed in terrupt mechanism. 0: disable tx delayed interrupt mechanism. 1b0 set to 0 will disable this feature 7b0 8b0 1b set to 0 will disable this feature 7b0 set to 0 will disable this feature. 8b0 32b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 108 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_max_cnt0: tx_max_cnt0 register (offset: 0x14) bits type name description initial value 31:12 - - reserved 20b0 12b0 20b0 12b0 20b0 12b0 32b0 20b0 12b0 20b0 12b0 20b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 109 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_base_ptr2: tx_base_ptr2 register (offset: 0x40) bits type name description initial value 31:0 r/w tx_base_ptr2 point to the base address of tx_ring2 (4 - dword aligned address) 32b0 20b0 12b0 20b0 12b0 20b0 32b0 20b0 12b0 20b0 12b0 20b0 2b0 6b111111 2b0 6b111111 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 110 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years bit[0]: pause q2 when pse p0 low q full 15:14 - - reserved 2b0 13:8 r/w pdm_fc_def_q1 q1 flow control pause condition bit[5]: pause q1 when pse p2 high q full bit[4]: pause q1 when pse p2 low q full bit [3]: pause q1 when pse p1 high q full bit[2]: pause q1 when pse p1 low q full bit[1]: pause q1 when pse p0 high q full bit[0]: pause q1 when pse p0 low q full 6b111111 7:6 - - reserved 2b0 5:0 r/w pdm_fc_def_q0 q0 flow control pause condition bit[5]: p ause q0 when pse p2 high q full bit[4]: pause q0 when pse p2 low q full bit[3]: pause q0 when pse p1 high q full bit[2]: pause q0 when pse p1 low q full bit[1]: pause q0 when pse p0 high q full bit[0]: pause q0 when pse p0 low q full 6b111111 3.17.3.7 register de scription C frame engine counters (base: 0x1010.0400) counter & meter table 0x000 ppe_ac_bcnt0 ppe accounting group #0 byte counter 0x004 ppe_ac_pcnt0 ppe accounting group #0 packet counter 0x1f8 ppe_ac_bcnt63 ppe accounting group #63byte counte r 0x1fc ppe_ac_pcnt63 ppe accounting group #63 packet counter 0x200 ppe_mtr_cnt0 - - 0x2fc ppe_mtr_cnt63 - 0x300 gdma_tx_gbcnt0 transmit good byte count for gdma port#1&2 0x304 gdma_tx_gpcnt0 transmit good pkt count for gdma port#1&2 (not includi ng flow control frames) 0x308 gdma_tx_skipcnt0 transmit skip count for gdma port#1&2 0x30c gdma_tx_colcnt0 transmit collision count for gdma port#1&2 0x310 C 0x31c reserved - 0x320 gdma_rx_gbcnt0 received good byte count for gdma port#1&2 0x324 gdma_r x_gpcnt0 received good pkt count for gdma port#1&2 (not including flow control frames) 0x328 gdma_rx_o ercnt0 received overflow error pkt count for gdma port#1&2 0x32c gdma_rx_fercnt0 received fcs error pkt count for gdma port#1&2 0x330 gdma_rx_sercnt0 r eceived too short error pkt count for gdma port#1&2 0x334 gdma_rx_lercnt0 received too long error pkt count for gdma port#1&2 0x338 gdma_rx_cercnt0 received ip/tcp/udp checksum error pkt count for gdma port#1&2 0x33c reserved - free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 111 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.18 ethernet switch 3.18.1 featur es ? support ieee 802.3 full duplex flow control ? 5 10/100mbps phy + 1 10/100/1000mbps rgmii/mii/reverse mii ? support spanning tree port states ? support 1k - mac address table with direct or xor hash ? qos ? four priorities queues per port ? packet classification based on incoming port, ieee 802.1p or ip tos/dscp ? strict - priority queue (pq) and weighted round robin (wrr) ? vlan ? port base vlan ? double vlan tagging ? 802.1q tag vlan ? 16 vids ? mac address table read and write - able ? mac security C locking a mac address to a incomin g port ? mac clone support C hash with vid ? igmp support ? broadcast storm prevention free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 112 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.18.2 block diagram fig. 3 - 18 - 1 ethernet switch block diagram d m a m a c d m a m a c d m a m a c d m a m a c d m a m a c g d m a g m a c 5 p o r t s f e p h y p 0 p 1 p 2 p 3 p 4 l i n k t a b l e l i n k m a n a g e m e n t d a t a b u f f e r d a t a m a n a g e m e n t a d d r e s s t a b l e a d d r e s s m a n a g e m e n t b r i d g e g d m a p 6 ( g 1 ) f r a m e e n g i n e p 5 ( g 0 ) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 113 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.18.3 register description (base: 0x1011.0000) isr: interrupt status register (offset: 0x00) bits type name description initial value 31:30 ro - reserved 3b0 this bit indicating that p5 dont transmit packet for 3 1b0 1b0 1b0 1b0 1b0 1b0 1b0 2b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 14b0 1b0 1b1 1b1 1b1 1b1 1b1 1b 1b1 1b1 1b1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 114 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 21 r/w sw_int_mask_21 reserved 1b1 20 r/w sw_int_mask_20 port6 queue full 1b1 19 r/w sw_int_mask_19 port5 queue full 1b1 18 r/w sw_int_mask_18 port4 queue full 1b1 17 r/w sw_int_mask_17 port3 queue full 1b1 16 r/w sw_int_mask_16 port2 queue full 1b1 15 r/w sw_int_mask_15 port1 queue full 1b1 14 r/w sw_int_mask_ 14 port0 queue full 1b1 13 r/w sw_int_mask_13 reserved 1b1 12 r/w sw_int_mask_12 reserved 1b1 11 r/w sw_int_mask_11 reserved 1b1 10 r/w sw_int_mask_10 reserved 1b1 9 r/w sw_int_mask_9 reserved 1b1 8 r/w sw_int_mask_8 reserved 1b1 7 r/w sw_int _mask_7 reserved 1b1 6 r/w sw_int_mask_6 reserved 1b1 5 r/w sw_int_mask_5 reserved 1b1 4 r/w sw_int_mask_4 reserved 1b1 3 r/w sw_int_mask_3 reserved 1b1 2 r/w sw_int_mask_2 reserved 1b1 1 r/w sw_int_mask_1 reserved. 1b1 0 r/w sw_int_mask_0 re served 1b1 fct0: flow control threshold 0 (offset:0x08) bits type name description initial value 31:24 r/w fc_rls_th flow control release threshold flow control is off when the global queue block counts is greater than the thr eshold 8d255 8d200 drop release threshold packets will stop dropping when the global queue block counts is greater than the threshold 8d110 drop set threshold packets will start dropping when the global queue block counts is less than the threshold. 8d90 24d0 8d20 C 0 (offset: 0x10) bits type name description initial value 31:28 - - reserved 4d0 4d15 ? 8d0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 115 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 15:12 r/w vo_num the proportional number of wrr ? after transmit exactly the number of packets then proceed to next queue, if equal to 0, force to unlimited mode 4d0 11:8 r/w cl_num the proportional number of wrr ? after transmit exactly the number of packet then proceed to nex t queue. 4d0 7:4 r/w be_num the proportional number of wrr ? after transmit exactly t he number of packet then proceed to nex t queue. 4d0 3:0 r/w bk_num the proportional number of wrr ? after transmit exactly the number of packet then proceed to nex t queue. 4d0 pfc1: priority flow control C 1 (offset: 0x14) bits type name description ini tial value 31 r/w p6_use_q1 _en port6 only use q1 enable 1d0 7d0 8d0 2b01 by setting this register to force per ports default priority. 2b01 by setting this register to force per ports default priority. 2b01 ports default priority. 2b01 by setting this register to force per ports default priority. 2b01 by setting this register to force per ports default priority. 2b01 by setting this register to force per ports default priority. 2b01 by setting this register to force per ports default priority. 2b01 C 2 (offset: 0x18) bits type name descri ption initial value 31:24 r/w pri_th_vo voice threshold C 8d3 8 8d3 C 8d3 C 0 (offset: 0x1c) bits type name description initial value 31:9 ro - reserved 23d0 9h16b free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 116 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years gqs1: global queue status C 1 (offset: 0x20) bits type name descri ption initial value 31:24 ro outque_full_vo congested voice queue the corresponding congested low queue 8d0 8d0 8d0 8d0 29b0 1b0 1b0 1b0 10d0 3d0 7d0 4d0 d0 1b0 1b0 1b0 16b0 16bx type name description initial value 31:0 ro mac_ad_ser1 read mac address [47:16] 32b0 10d0 3d0 1b1 7b0 4b0 3b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 117 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1 ro w_mac_done mac write done 1: mac address write ok, (read_clear) 1b0 0 r/w w_mac_cmd mac address write command 1: the mac write data is ready and write to mac table now, self_clear 1b0 wmad1 : wt_mac_ad1 (offset: 0x38) bits type name description initial value 31:16 ro - reserved 16b0 16h0 type name description initial value 31:0 r/w w_mac_47_16 write mac address [47:16] 32b0 type name description initial value 31:24 ro - reserved 8d0 12d1 12d1 type name description initial value 31:24 ro - reserved 8d0 12d1 12d1 type name description initial value 31:24 ro - reserved 8d0 12d1 12d1 type name description initial value 31:12 ro - reserved 20d0 12d1 type name description initial value 31:24 ro - reser ved 8d0 12d2 12d1 type name description initial value 31:24 ro - reserved 8d0 12d4 12d3 type name description initial value 31:24 ro - reserved 8d0 12d6 12d5 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 118 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years vlani3: vlan identifier 3 (offset: 0x5c) bits type name description initial value 31:24 ro - reserved 8d0 12d8 12d7 type name description initial value 31:24 ro - reserved 8d0 12d10 12d9 type name description initial value 31:24 ro - reserved 8d0 12d12 12d11 type name descri ption initial value 31:24 ro - reserved 8d0 12d14 12d13 type name description initial value 31:24 ro - reserved 8d0 12d16 12d15 type name description initial value 30:24 r/w vlan_memset_3 vlan 3 member port 8hff vlan 2 member port 8hff vlan 1 member port 8hff vlan 0 member port 8hff type name description initial value 30:24 r/w vlan_memset_7 vlan 7 member port 8hff vlan 6 member port 8hff vlan 5 member port 8hff vlan 4 member port 8hff type n ame description initial value 30:24 r/w vlan_memset_11 vlan 11 member port 8hff vlan 10member port 8hff vlan 9 member port 8hff vlan 8 member port 8hff type name description initial value 30:24 r/w vlan_memset_15 vlan 15 member port 8hff vlan 14 member port 8hff vlan 13 member port 8hff vlan 12 member port 8hff free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 119 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years poa: port ability (offset: 0x80) bits type name description initial value 31 ro g1_link port 6 link 1=up, 0=down 1b0 1b0 5b0 2b0 2b0 5b0 7h00 2b0 2b0 5b0 type name description initial value 31:27 r/w force_mode port4 ~ port 0 force mode 5d0 port 4 ~ port 0 phy link 1=up, 0=down 5b0 1d0 5d0 3d0 port4 ~ port0 duplex , 1= full duplex, 0=half duplex 5d0 3d0 port4 ~ port0 speed: 1=100m, 0=10m 5b0 type name description initial value 31:10 ro - reserved 22b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 120 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 6:0 ro secured_st security stat us 1= has intruder coming if turn on the sa_secured mode, read clear 7b0 socpc: soc port control (offset: 0x8c) bits type name description initial value 31:26 ro - reserved 6b0 1b1 2b0 7h7f 1b0 7h7f 1b0 7h7f 2b0 1b1 1b1 5h1f 7h0 1b0 7h7f 1b0 7h7f type name description initial value 31:23 ro - reserve d 9d0 7d0 1d0 7b0 1d0 0: dont care sa match, the packets sa need match, otherwise discard the 7b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 121 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years poc2: port control 2 (offset: 0x98) bits type name description initial value 31 ro - reserved 1b0 1b0 1b0 6b0 7b0 1b0 7h7f 8h0 type name des cription initial value 31:29 ro - reserved 3b0 2b0 2b00 2b0 2b0 1b0 2b10 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 122 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 15:12 r/w bp_jam_cnt back pressure jam number the consecutive jam time when back pressure, default 10 packet jam then one no - jam 4b1010 11 r/w disable tx backoff disable the collision back off timer 1: re - transmit immediately after collision, 1b0 10:9 r/w address_hash_alg mac address hashing algorithm 00: direct mode, using last 10 - bit as hashing address 01: xor48 mode 10: xor32 mode, 11:r eserved 2b0 8 r/w dis_pkt_tx_abort 1: disable collision 1 6 packet abort and late collision abort 0: enable both abort 1b1 7:6 r/w pkt_max_len maximum packet length 00: 1536, 01: 1518, 10: 1522, 11: reserved 2b0 5:4 r/w bc_storm_prev broadcast storm prevention 00: disable , bc will be blocked, if (01: 64 , 1 0: 48, 11: 32) bc blocks in queue 2b0 3:0 r/w aging interval aging timer 0000: disable age, 1xxx: fast age 0001: 300sec , 0010: 600 0111: 38400sec 4d1 strt: switch reset (offset: 0xa0) bits type name description initial value 31:0 wo reset_sw reset switch engine, data, address, link memory , cpu port and ahb interface when write. 32b0 type name description initial value 31:4 ro - reserved 28d0 4b0000 4b0001: 100m speed 4b0010: duplex 4b0011: activity 4b0100: collision 4b0101: link/activity 4b0110: duplex/collsion 4b0111: 10m speed/activity 4b1000: 100m speed/activity 4b0101 type name description in itial value 31:4 ro - reserved 28b0 4b0101 type name description initial value 31:4 ro - reserved 28b0 4b0101 type name description initial value 31:4 ro - reserved 28b0 4b0101 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 123 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ledp4 : led port4 (offset: 0xb4) bits type name description initial value 31:4 ro - reserved 28b0 4b0101 24b0 buffer starvation threshold switch wi ll interrupt cpu when the global queue block counts is less than the threshold for 3 seconds. 8d30 16b0 16b0 type name description initial value 31:16 rw wt_nway_data the data be written into the phy 17b0 1b0 1b0 1b0 5b0 3b0 5b0 type name description initial value 31:16 ro rd_data the read data 15b0 14b0 1b0 1b0 type name description initial value 31:30 ro - reserve d 2b0 1b0 5d5 2d01 2d01 1d0 1b0 2b0 1b0 1b0 1b0 1b0 1b0 1b0 2b11 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 124 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1x: for tx, x1: for rx 5 r/w force_ rgmii_dpx1 force port 6 duplex 1b1 4 r/w force_ rgmii_dpx0 force port 5 duplex 1b0 3:2 r/w force_ rgmii_spd1 force port 6 speed 1x: 1gmhz, 01: 100mhz, 00: 10mhz 2b10 1:0 r/w force_ rgmii_spd0 force port 5 speed 1x: 1gmhz, 01: 100mhz, 00: 10mhz 2b0 fct2: flow control threshold 2 (offset: 0xcc) bits type name description initial value 31:18 ro - reserved 14d0 if the global queue pointer higher than the threshold. the mu st drop condition will be released. 5d5 5d3 2b0 mc packets per port threshold. 6d12 type name description initial value 31:24 ro - reserved 8b0 9b0 link control background block counter monitor 10b0 5b0 type name description initial value 31:18 ro - reserved 14b0 9b0 link control background block counter monitor 9b0 type name description initial value 31:24 r/w bridge ipg bridge ipg byte count 8d64 18d0 3b0 3d0 type name description initial value 31:16 ro - reserved 16b0 9bx 1bx 1bx 1bx 1bx 1bx free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 125 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1 ro dt_ram_test_ done data buffer ram test done 1bx 0 ro dt_ram_test_ fail data buffer ram test fail 1bx ppc: port 6 packet counter (offset: 0x e0) bits type name description initial value 31:16 ro sw2fe_cnt switch to frame engine packet counter 16b0 6b0 1b0 1b0 6b0 9b0 7b0 b0 1b0 1b0 3b0 7b0 type name description initial value 31:16 ro bad_pkt_cnt0 port 0 receive bad packet counter 16b0 16b0 type name description initial value 31:16 ro bad_pkt_cnt1 port 1 receive bad packet counter 16b0 16b0 type name description initial value 31:16 ro bad_pkt_cnt2 port 2 receive bad packet counter 16b0 16b0 type name description in itial value 31:16 ro bad_pkt_cnt3 port 3 receive bad packet counter 16b0 16b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 126 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years p4pc: port 4 packet counter (offset: 0xf8) bits type name description initial value 31:16 ro bad_pkt_cnt4 port 4 r eceive bad packet counter 16b0 16b0 type name description initial value 31:16 ro bad_pkt_cnt5 port 5 receive bad packet counter 16b0 16b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 127 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.18.4 mii control register these registers could be accessed by pcr0 (phy control register 0) and pcr1 indirectly. among them, phy reg0 ~1 and 4~6 are unique for each port. phy reg2~3 are common for all 5 ports. legend: sc: self - clearing, rc: read - clearing ll: latching low, lh: latching high r/w: read/write, ro : read - only cr address: 00(d00) reset state:3100 bit read/write name description default 15 r/ w; sc mr_main_re set 1=reset: 0 =nor mal, reset all digital logic, except phy_reg 1h0 1h0 mr_autoneg_enable = 1b0 1h1 1h1 1h0 1h0 1h0 mr_autoneg_enable = 1b0 1h1 bit read/write name description d efault 15 ro 100 base t4 not supported 1h0 1h 1h1 1h1 1h1 1h0 1h0 2h0 1h1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 128 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5 ro mr_autoneg_complete 1 = auto - negotiate completed, 0 = au to - negotiate incomplete 1h0 4 ro - reserved 1h0 3 ro autoneg ability 1 = phy can auto - negotiate, 0 = phy cannot auto - negotiate 1h1 2 ro/ll link status 1 = link is up, 0 = link is down 1h0 1 ro/lh; rc jabber detect 1 = jabber condition detected 1h0 0 ro extended capability 1=extended register capabilities, 0=basic register set capabilities only 1h1 phy id entifier register cr address: 02(d02) reset state: 00c3 bit read/write name description default 15:0 ro phy_id[31 - 16] oui (bits 3 - 18). ralink oui =000c43 16h00c3 bit read/write name de scription default 15:10 ro phy_id[15 - 10] oui (bits 19 - 24) 6h02 manufacturers model number (bits 5 6h00 4h0 bit read/write name description default 15 r0 next page enable 1=set to use nex t page: 0 =not to use next page 1h0 1h0 1h0 2h0 1h1 1h0 1h1 1h1 1h1 1h1 5h01 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 129 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years auto - negotiation link partner (lp) ability register cr address: 05(d05) reset state: 0000 bit read/write name description default 15 r o next page 1=link partner is requesting next page function 0=base page is requested. 1h0 1h0 1h0 2h0 1h0 1h0 1h0 1h0 1h0 1h0 5h00 bit r/w/type name description default 15:5 ro reserved no meaning 11 1h 1h 1h 1h 1h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 130 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.19 usb otg controller & phy 3.19.1 features ? support usb host/device dual mode ? complies with the on - the - go supplement to the usb 2.0 specification (revision 1.0a) ? operates in high - speed (hs, 480 - mbps ), full - speed (fs, 12 - mbps) and low - speed (ls, 1.5 - mbps) modes ? supports up to 4 bidirectional endpoints, including control endpoint 0 ? supports up to 4 host channels. ? supports a generic root hub ? includes automatic ping capabilities ? supports internal dma mo des ? includes usb power management features ? includes power - saving features (clock gating, two power rails for advanced power management) ? supports packet - based, dynamic fifo memory allocation for endpoints for small fifos , and flexible, efficient use of ram pr ovides support to change an endpoints fifo memory size during transfers 3.19.2 block diagram fig. 3 - 19 - 1 1.1 usb otg controller & phy block diagram free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 131 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.19.3 register description (base: 0x1 01c .0000) gotgctl : otg control and status register (offset: 0x00 0 ) bits typ e name description mode initial value 31: 2 0 - - reserved - 12 ? 1b0: b ? 1b1: b 1b0 ? 1b0: a ? 1b1: a 1b0 ? 1b0: long debounc e time, used for physical connections (100 ms + 2.5 s) ? 1b1: short debounce time, used for soft connections (2.5 s) 1b0 ? 1b0: the dwc_otg core is in a ? 1b1: the dwc_otg core is in b 1b0 b0 ? 1b0: hnp is not enabled in the application ? 1b1: hnp is enabled in the application 1b0 ? 1b0: host set hnp is not enabled ? 1b1: host set hnp is enabled 1b0 ? 1b0: no hnp r equest ? 1b1: hnp request 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 132 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years core clears this bit when the hnp request (hnpreq) bit in th is register is set. ? 1b0: host negotiation failure ? 1b1: host negotiation success 7:2 - - reserved - 4 h 0 1 r/w sesreq session request the application sets this bit to initiate a session request on the usb. the application can clear this bit by writing a 0 when the host negotiation success status change bit in the otg interrupt register (gotgint.hstnegsucstschng) is set. the core clears this bit when the hstnegsucstschng bit is cleared. if you use the usb 1.1 full - speed serial trans ceiver interface to initiate the session request, the application must wait until the vbus discharges to 0.2 v, after the b - session valid bit in this register (gotgctl.bsesvld) is cleared. this discharge time varies between different phys and can be obtai ned from the phy vendor. ? 1b0: no session request ? 1b1: session request device only 1b0 0 ro sesreqscs session request success the core sets this bit when a session request initiation is successful. ? 1b0: session request failure ? 1b1: session re quest success device only 1b0 gotgctl : otg interrupt register (offset: 0x00 4 ) bits type name description mode initial value 31: 2 0 - - reserved - 12 1b0 1b0 1b0 7b0 b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 133 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 8 r _ss_ wc sesreqsucsts chng session request success status change the core sets this bit on the success or failure of a session request. the application must read the session request success bit in the otg control and status register (gotgctl.sesreqscs) to check for success or failure. host and device 1b0 7:3 - - reserved - 6 h 0 2 r _ss_ wc sesenddet session end detected the core sets this bit when the utmiotg_bvalid signal is deasserted. host and device 1b0 1:0 - - reserved - 2h0 gahbcfg: core ahb configuration register (offset: 0x00 8 ) bits type name description mode ini tial value 31: 9 - - r eserved - 22 ? 1b0: gintsts.p ? 1b1: gintsts.ptxfemp interrupt indicates that 1b0 ? 1b0: gintsts.nptxfemp interrupt indicates that ? 1b1: gintsts.nptxfemp interrupt ? 1b0: diepintn.txfemp interrupt indicates that the ? 1b1: diepintn.txfemp interrupt indicates that the 1b0 1b0 ? 1b0: core operates in slave mode ? 1b1: core operates in a dma mode free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 134 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 4:1 r/w hbstlen burst length/type this field is used in both external and internal dma modes. in external dma mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the external dma controller interface to synopsys dw_ahb_dmac or arm primecell. external dma mode defines the dma burst length in terms of 32 - bit words: ? 4b0000: 1 word ? 4b0001: 4 words ? 4b0010: 8 words ? 4b 0011: 16 words ? 4b0100: 32 words ? 4b0101: 64 words ? 4b0110: 128 words ? 4b0111: 256 words ? others: reserved internal dma mode ahb master burst type: ? 4b0000 single ? 4b0001 incr ? 4b0011 incr4 ? 4b0101 incr8 ? 4b0111 incr16 ? others: reserved host and device 4 b0 0 r/w glblintrmsk global interrupt mask the application uses this bit to mask or unmask the interrupt line assertion to itself. irrespective of this bits setting, the interrupt status registers are updated by the core. ? 1b0: mask the interrupt assertion to the application. ? 1b1: unmask the interrupt assertion to the application. host and device 1b0 gusbcfg: core usb configuration register (offset: 0x00 c ) bits type name description mode initial value 31 r/w corrupt tx packet corrupt tx packet this bit is for debug purposes only. never set this bit to 1. host and device 1b0 ? 1b0 : ? 1b1 : force device mode. 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 135 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 29 r /w fo rcehstmode writing a 1 to this bit will force the core to host mode irrespective of utmiotg_iddig input pin. ? 1b0 : nor mal mode. ? 1b1 : force host mode. after setting the force bit, the application must wait at least 25 ms before the change to tak e effect. when the simulation is in scale down mode, waiting for 500 us is sufficient. host and device 1b0 28:23 - - r eserved - 6 h 0 22 r/w termseldlpu lse ulpi external vbus indicator this bit indicates to the ulpi phy to use an external vbus over - curr ent indicator. ? 1b0: phy uses internal vbus valid comparator. ? 1b1: phy uses external vbus valid comparator. (valid only when rtl parameter otg_hsphy _interface = 2 or 3) device only 1 b 0 21 r/w ulpiextvbusi ndicator ulpi external vbus indicator th is bit indicates to the ulpi phy to use an external vbus over - current indicator. ? 1b0: phy uses internal vbus valid comparator. ? 1b1: phy uses external vbus valid comparator. (valid only when rtl parameter otg_ hsphy_ interface = 2 or 3) host only 1b0 20 r/w ulpiextvbus drv ulpi external vbus drive this bit selects between internal or external supply to drive 5v on vbus, in ulpi phy. ? 1b0: phy drives vbus using internal charge pump (default). ? 1b1: phy drives vbus using external supply . (valid only when rtl parameter otg_ hsp hy_ interface = 2 or 3) host only 1b0 19 r/w ulpiclksusm ulpi clock suspendm this bit sets the clocksuspendm bit in the interface control register on the ulpi phy. this bit applies only in serial or carkit modes. ? 1b0: phy powers down internal clock during suspend. ? 1b1: phy does not power down internal clock. (valid only when rtl parameter otg_ hsphy_ interface = 2 or 3) host and device 1b0 18 r/w ulpiautores ulpi auto resume this bit se ts the autoresume bit in the interface control register on the ulpi phy. ? 1b0: phy does not use autoresume feature. ? 1b1: phy uses autoresume feature. (valid only when rtl parameter otg_hsphy _ interface = 2 or 3) host and device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 136 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 17 r/w ulpi fsls ulpi fs/ls selec the application uses this bit to select the fs/ls serial interface for the ulpi phy. this bit is valid only when the fs serial transceiver is selected on the ulpi phy. ? 1b0: ulpi interface ? 1b1: ulpi fs/ls serial interface (valid only when rtl parameters otg_hsphy_interface = 2 or 3 and otg_fsphy_interface = 1, 2, or 3) host and device 1b0 16 ro/r _w otgi2csel utmifs or i c interface selec the application uses this bit to select the i2c interface. ? 1b0: utmi usb 1.1 full - speed interface for otg signals ? 1b1: i2c interface for otg signals this bit is writable only if i2c and utmifs were specified for enable i2c interface? in coreconsultant (parameter otg_i2c_interface = 2). o ther wise, reads return 0. host and device 1b0 15 r/w phylpwrclks el phy low - power clock selec t selects either 480 - mhz or 48 - mhz (low - power) phy mode. in fs and ls modes, the phy can usually operate on a 48 - mhz clock to save power. ? 1b0: 480 - mhz internal pll clock ? 1b1: 48 - mhz external clock i n 480 mhz mode, the utmi interface operates at either 60 or 30 - mhz, depending upon whether 8 - or 16 - bit data width is selected. in 48 - mhz mode, the utmi interface operates at 48 mhz in fs mode and at either 48 or 6 mhz in ls mode (depending on the phy vend or). this bit drives the utmi_fsls_low_power core output signal, and is valid only for utmi+ phys. host and device 1b0 14 - - reserved - 1b0 13:10 r/w usbtrdtim usb turnaround time sets the turnaround time in phy clocks. specifies the response time for a mac r equest to the packet fifo controller (pfc) to fetch data from the dfifo (spram). this must be programmed to ? 4h5: when the mac interface is 16 - bit utmi+ . ? 4h9: when the mac interface is 8 - bit utmi+ . note: the values above are calculated for t he minimum ahb fr equency of 30 mhz. usb turnaround time is critical for certification where long cables and 5 - hubs are used, so if you need the ahb to run at less than 30 mhz, and if usb turnaround time is not critical, these bits can be programmed to a la rger value. see choosing the value of gusbcfg. usbtrdtim on page 411. device only 4h5 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 137 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 9 ro/r _w hnpcap hnp - capable the application uses this bit to control the dwc_otg cores hnp capabilities. ? 1b0: hnp capability is not enabled. ? 1b1: hnp capabil ity is enabled. this bit is writable only if an hnp mode was specified for mode of operation in coreconsultant (parameter otg_mode). otherwise, reads return 0. host and device 1b0 8 ro/r _w srpcap srp - capable the application uses this bit to control the dwc_otg core srp capabilities. if the core operates as a non - srp - capable b - device, it cannot request the connected a - device (host) to activate vbus and start a session. ? 1b0: srp capability is not enabled. ? 1b1: srp capability is enabled. this bit is writable only if an srp mode was specified for mode of operation in coreconsultant (parameter otg_mode). otherwise, reads return 0. host and device 1b0 7 r/w ddrsel ulpi ddr selec t the application uses this bit to select a single data rate (sdr) or doub le data rate (ddr) or ulpi interface. ? 1b0: single data rate ulpi interface, with 8 - bit - wide data bus ? 1b1: double data rate ulpi interface, with 4 - bit - wide data bus host and device 1b0 6 wo/r _w physel usb 2.0 high - speed phy or usb 1 .1 full - speed serial transceiver select the application uses this bit to select either a high - speed utmi+ or ulpi phy, or a full - speed transceiver. ? 1b0: usb 2.0 high - speed utmi+ or ulpi phy ? 1b1: usb 1.1 full - speed serial transceiver if a usb 1.1 full - speed serial transceiver interface was not selected in coreconsultant (parameter otg_fsphy_interface = 0), this bit is always 0, with write only access. if a high - speed phy interface was not selected in coreconsultant (parameter otg_hsphy_interface = 0), this bit is always 1, with write only access. if both interface types were selected in coreconsultant (parameters have non - zero values), the application uses this bit to select which interface is active, and access is read and write. host and device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 138 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5 wo/r _w fsintf full - speed serial interface select the application uses this bit to select either a unidirectional or bidirectional usb 1.1 full - speed serial transceiver interface. ? 1b0: 6 - pin unidirectional full - speed serial interface ? 1b1: 3 - pin bidirectional full - speed serial interface if a usb 1.1 full - speed serial transceiver interface was not selected in coreconsultant (parameter otg_fsphy_interface = 0), this bit is always 0, with write only access. if a usb 1.1 fs interface was select ed in core consultant (parameter otg_fsphy_interface ! = 0), then the application can set this bit to select between the 3 - and 6 - pin interfaces, and access is read and write. host and device 1b0 4 ro/r _w ulpi_utmi_ sel ulpi or utmi+ select the applicati on uses this bit to select either a utmi+ interface or ulpi interface. ? 1b0: utmi+ interface ? 1b1: ulpi interface this bit is writable only if utmi+ and ulpi was specified for high - speed phy interface(s) in coreconsultant configuration (parameter otg_h sphy_interface = 3). otherwise, reads return either 0 or 1, depending on the interface selected using the otg_hsphy_interface parameter. host and device 1b0 3 ro/r _w phyif phy interface the application uses this bit to configure the core to support a ut mi+ phy with an 8 - or 16 - bit interface. when a ulpi phy is chosen, this must be set to 8 - bit mode. ? 1b0: 8 bits ? 1b1: 16 bits this bit is writable only if utmi+ and ulpi wer e selected in coreconsultant configuration (parameter otg_hsphy_dwidth = 3). o ther wise, this bit returns the value for the power - on interface selected during configuration. host and device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 139 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2:0 r/w toutcal hs/fs timeout calibration the number of phy clocks that the application programs in this field is added to the high - speed/ full - speed interpacket timeout duration in the core to account for any additional delays introduced by the phy. this can be required, because the delay introduced by the phy in generating the linestate condition can vary from one phy to another. the usb s tandard timeout value for high - speed operation is 736 to 816 (inclusive) bit times. the usb standard timeout value for full - speed operation is 16 to 18 (inclusive) bit times. the application must program this field based on the speed of enumeration. the number of bit times added per phy clock are: high - speed operation: ? one 30 - mhz phy clock = 16 bit times ? one 60 - mhz phy clock = 8 bit times full - speed operation: ? one 30 - mhz phy clock = 0.4 bit times ? one 60 - mhz phy clock = 0.2 bit times ? one 48 - mhz p hy clock = 0.25 bit times host and device 3h0 grstctl: cor e reset register (offset: 0x0 10 ) bits type name description mode initial value 31 r/o ahbidle ahb master idle indicates that the ahb master state machine is in the idle condition. host and device 1b1 1b0 19h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 140 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 10:6 r/w txfnum txfifo number this is the fifo number that must be flushed using the txfifo flush bit. this field must not be changed until the core clears the txfifo flush bit. ? 5h0: - non - periodic txfifo flush in host mode - non - periodic txfifo flush in device mode when in shared fifo operation - tx fifo 0 flush in device mode when in dedicated fifo mode ? 5h1: - periodic txfifo flush in host mode - periodic txfifo 1 flush in device mode when in shared fifo operation - txfifo 1 flush in device mode when in dedicated fifo mode ? 5h2: - periodic txfifo 2 flush in device mode when in shared fifo operation - txfifo 2 flush in device mode when in dedicated fifo mode ... ? 5hf: - periodic txfifo 15 flush in device mode when in shared fifo operation - txfifo 15 flush in device mode when in dedicated fifo mode ? 5h10: flus h all the transmit fifos in device or host mode. host and device 5h0 5 r _ ws _ sc txfflsh txfifo flush this bit selectively flushes a single or all transmit fifos, but cannot do so if the core is in the midst of a transaction. the application must write this bit only after checking that the core is neither writing to the txfifo nor reading from the txfifo. verify using these registers: ? read nak effective interrupt ensures the core is not reading from the fifo ? write grstctl.ahbidle ensures the core is not writing anything to the fifo. flushing is normally recommended when fifos are reconfigured or when switching between shared fifo and dedicated transmit fifo operation. fifo flushing is also recommended during device endpoint disable. the application must wait until the core clears this bit before performing any operations. this bit takes eight clocks to clear, using the slower clock of phy_clk or hclk. host and device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 141 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 4 r _ ws _ sc rxfflsh rxfifo flush the application can flush the entire rxfifo using this bit, but must first ensure that the core is not in the middle of a transaction. the application must only write to this bit after checking that th e core is neither reading from the rxfifo nor writing to the rxfifo. the applica tion must wait until the bit is cleared before performing any other operations. this bit requires 8 clocks (slowest of phy or ahb clock) to clear. host and device 1b0 3 r _ ws _ sc intknqflsh in token sequence learning queue flush this bit is valid only if otg_en_ded_tx_fifo = 0. the application writes this bit to flush the in token sequence learning queue. device only 1b0 2 r _ ws _ sc frmcntrrst host frame counter reset the application writes this bit to reset the (micro) frame number counter inside th e core. when the (micro)frame counter is reset, the subsequent sof sent out by the core has a (micro) frame number of 0. host only 1b0 1 r _ ws _ sc hsftrst hclk soft reset the application uses this bit to flush the control logic in the ahb clock domain. only ahb clock domain pipelines are reset. ? fifos are not flushed with this bit. ? all state machines in the ahb clock domain are reset to the idle state after terminating the transactions on the ahb, following the protocol. ? csr control bits used by t he ahb clock domain state machines are cleared. ? to clear this interrupt, status mask bits that control the interrupt status and are generated by the ahb clock domain state machine are cleared. ? because interrupt status bits are not cleared, the appl ication can get the status of any core events that occurred after it setthis bit. this is a self - clearing bit that the core clears after all necessary logic is reset in the core. this can take several clocks, depending on the cores current state. host an d device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 142 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0 r_ws _sc csftrst core soft reset resets the hclk and phy_clock domains as follows: ? clears the interrupts and all the csr registers except the following register bits: - pcgcctl.rstpdwnmodule - pcgcctl.gatehclk - pcgcctl.pwrclmp - pcgcct l.stoppphylpwrclkselclk - gusbcfg.phylpwrclksel - gusbcfg.ddrsel - gusbcfg.physel - gusbcfg.fsintf - gusbcfg.ulpi_utmi_sel - gusbcfg.phyif - hcfg.fslspclksel - dcfg.devspd - ggpio ? all module state machines (except the ahb slave unit) are reset to the idle state, and all the transmit fifos and the receive fifo are flushed. ? any transactions on the ahb master are terminated as soon as possible, after gracefully completing the last data phase of an ahb transfer. any transactions on the usb are terminat ed immediately. the application can write to this bit any time it wants to reset the core. this is a self - clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the curre nt state of the core. onc e this bit is cleared software must wait at least 3 phy clocks before doing any access to the phy domain (synchronization delay). software must also must check that bit 31 of this register is 1 (ahb master is idle) before start ing any operation.typically software reset is used during software development and also when you dynamically change the phy selection bits in the usb configuration registers listed above. when you change the phy, the corresponding clock for the phy is selected and used in the phy domain. once a new clock is selected, the phy domain has to be reset for proper operation. host and device 1b0 gintsts: cor e interrupt register (offset: 0x0 14 ) bits type name description mode initial value 31 r_ss_ wc wku pint resume/remote wakeup detected interrupt in device mode, this interrupt is asserted when a resume is detected on the usb. in host mode, this interrupt is asserted when a remote wakeup is detec ted on the usb. for more information on how to use this in terrupt, see partial power programming model on page 417. 1b0 host 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 143 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years wc in host mode, this interrupt is asserted when a session request is detected from the device. in device mode, this interrupt is asserted when the utmiotg_bvalid signal goes high. for more information on how to use this interrupt, see partial power - down and clock gating programming model on page 417. and device 29 r_ss_ wc di sconnint disconnect detected interrupt asserted when a device disconnect is detected. host only 1b0 28 r_ss_ wc conidstschng connector id status change the core sets this bit when ther e is a change in connector id status. host and device 1b0 27 - - re served - 1b0 26 r o ptxfemp periodic txfifo empty asserted when the periodic transmit fifo is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. the half or completely empty status is det ermined by the periodic txfifo empty level bit in the core ahb configuration register (gahbcfg.ptxfemplvl). host only 1b1 25 r o hchint host channels interrupt the core sets this bit to indicate that an interrupt is pending on one of the channels of th e core (in host mode). the application must read the host all channels interrupt (haint) register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding host channel - n interrupt (hcintn) register to determine the exact cause of the interrupt. the application must clear the appropriate status bit in the hcintn register to clear this bit. host only 1b0 24 r o prtint host port interrupt the core sets this bit to indicate a change in port status of on e of the dwc_otg core ports in host mode. the application must read the host port control and status (hprt) register to deter mine the exact event that caused this interrupt. the application must clear the appropriate status bit in the host port control and status register to clear this bit. host only 1b0 23 - - reserved - 1b0 22 r_ss_ wc fetsusp data fetch suspended this interrupt is valid only in dma mode. this interrupt indicates that the core has stopped fetching data for in endpoints due to the un availability of txfifo space or request queue space. this interrupt is used by the application for an endpoint mismatch algorithm. for example, after detecting an endpoint mismatch, the application: device only 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 144 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? sets a global non - periodic in nak handshake ? disables in endpoints ? flushes the fifo ? deter mines the token sequenc e from the in token sequence learning queue ? re - enables the endpoints ? clears the global non - periodic in nak handshake if the global non - periodic in nak is cleared, the core has not yet fetch ed data for the in endpoint, and the in token is received: the core generates an in token r eceived when fifo empty interrupt. the otg then sends the host a nak r esponse. to avoid this scenario, the application can check the gintsts. fetsusp interrupt, which ensures that the fifo is full before clearing a global nak handshake. alternatively, the application can mask the in token received when fifo empty interrupt when clearing a global in nak handshake. 21 r_ss_ wc incomplp incomple te periodic transfer in host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current microframe. incomplete isochronous out transfer (incompisoout) the device mode, the cor e sets this interrupt to indicate that there is at least one isochronous out endpoint on which the transfer is not completed in the current microframe. this interrupt is asserted along with the end of periodic frame interrupt (eopf) bit in this register . host only device only 1b0 20 r_ss_ wc incompisoin incomplete isochronous in transfer the core sets this interrupt to indicate that there is at least one isochronous in endpoint on which the transfer is not completed in the current microframe. th is interrupt is asserted along with the end of periodic frame interrupt (eopf) bit in this register device only 1b0 19 ro oepint out endpoints interrupt the core sets this bit to indicate that an interrupt is pending on one of the out endpoints of the core (in device mode). the application must read the device all endpoints interrupt (daint) register to determine the exact number of the o ut endpoint on which the interrupt occurred, and then read the corresponding device out endpoint - n interrupt (doep intn) register to determine the exact cause of the interrupt. the application must clear the appropriate status bit in the corresponding doepintn register to clear this bit. device only 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 145 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 18 ro iepint in endpoints interrupt the core sets this bit t o indicate that an interrupt is pending on one of the in endpoints of the core (in device mode). the application must read the device all endpoints interrupt (daint) register to determine the exact number of the in endpoint on which the interrupt occurre d, and then read the corresponding device in endpoint - n interrupt (diepintn) r egister to determine the exact cause of the interrupt. the application must clear the appropriate status bit in the corresponding diepintn register to clear this bit. device on ly 1b0 17 r_ss_ wc epmis endpoint mismatch interrupt note: this interrupt is valid only in shared fifo operation. indicates that an in token has been received for a non - periodic endpoint, but the data for another endpoint is present in the top of the non - periodic transmit fifo and the in endpoint mismatch count programmed by the application has expired. device only 1b0 16 - - reserved - 1b0 15 r_ss_ wc eopf end of periodic frame interrupt indicates that the period specified in the periodic frame inter val field of the device configuration register (dcfg.perfrint) has been r eached in the current microframe. device only 1b0 14 r_ss_ wc isooutdrop isochronous out packet dropped interrupt the core sets this bit when it fails to write an isochronous out packet into the rxfifo because the rxfifo doesnt have enough space to accommodate a maximum packet size packet for the isochronous out endpoint. device only 1b0 13 r_ss_ wc enumdone enumeration done the core sets this bit to indicate that speed enume ration is complete. the application must read the device status (dsts) register to obtain the enumerated speed. device only 1b0 12 r_ss_ wc usbrst usb reset the core sets this bit to indicate that a reset is detected on the usb. device only 1b0 11 r _ss_ wc usbsusp usb suspend the core sets this bit to indicate that a suspend was detected on the usb. the core enters the suspended state when there is no activity on the phy_line_state_i signal for an extended period of time. device only 1b0 10 r_ss_ wc erlysusp early suspend the core sets this bit to indicate that an idle state has been detected on the usb for 3 ms. device only 1b0 9 r_ss_ wc i2cint i2c interrupt the core sets this interrupt when i2c access is completed on the host and device 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 146 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years i2c interface. this fi eld is used only if the i2c interface was enabled in coreconsultant (parameter otg_i2c_interface = 1). otherwise, reads return 0. 8 r_ss_ wc ulpickint ulpi carkit interrupt this field is used only if the carkit interface was enabled i n coreconsultant (parameter otg_ulpi_carkit = 1). otherwise, reads return 0. the core sets this interrupt when a ulpi carkit interrupt is received. the cores phy sets ulpi carkit interrupt in uart o audio mode. i2c carkit interrupt (i2cckint) this fiel d is used only if the i2c interface was enabled in coreconsultant (parameter otg_i2c_interface = 1). otherwise, reads return 0. the core sets this interrupt when a carkit interrupt is received the cores phy sets the i2c carkit interrupt in audio mode. ho st and device 1b0 7 ro goutnakeff global out nak effec tive indicates that the set global out nak bit in the device control register (dctl.sgoutnak), set by the application, has taken effect in the core. this bit can be cleared by writing the clear globa l out nak bit in the device control register (dctl.cgoutnak). device only 1b0 6 ro ginnakeff global in non - periodic nak effec tive indicates that the set global non - periodic in nak bit in the device control register (dctl.sgnpinnak), set by the applicati on, has taken effect in the core. that is, the core has sampled the global in nak bit set by the application. this bit can be cleared by clearing the clear global non - periodic in nak bit in the device control register (dctl.cgnpinnak). this interrupt does not necessarily mean that a nak handshake is sent out on the usb. the stall bit takes precedence over the nak bit. device only 1b0 5 ro nptxfemp non - periodic txfifo empty this interrupt is valid only when otg_en_ded_tx_fifo = 0. this interrupt is asse rted when the non - periodic txfifo is either half or completely empty, and there is space for at least one entry to be written to the non - periodic transmit request queue. the half or completely empty status is determined by the non - periodic txfifo empty l evel bit in the core ahb configuration register (gahbcfg.nptxfemplvl). host and device 1b1 4 ro rxflvl rxfifo non - empty indicates that ther e is at least one packet pending to be read from the rxfifo. host and device 1b0 3 r_ss_ wc sof start of (micro )frame in host mode, the core sets this bit to indicate that host and 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 147 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years an sof (fs), micro - sof (hs), or keep - alive (ls) is transmitted on the usb. the application must write a 1 to this bit to clear the interrupt. in device mode, in the core sets this bit to indica te that an sof token has been rec eived on the usb. the application can read the device status register to get the current (micro)frame number . this interrupt is seen only when the core is operating at either hs or fs. device 2 ro otgint o tg interrupt the core sets this bit to indicate an otg protocol event. the application must read the otg interrupt status (gotgint) r egister to deter mine the exact event that caused this interrupt. the application must clear the appropriate status bit in the gotgint register to clear this bit. host and device 1b0 1 r_ss_ wc modemis mode mismatch interrupt the core sets this bit when the application is trying to access: ? a host mode r egister, when the core is operating in device mode ? a device mode regi ster, when the core is operating in host mode the register access is completed on the ahb with an okay response, but is ignored by the core internally and doesnt affect the operation of the core. host and device 1b0 0 ro curmod current mode of opera tion indicates the current mode of operation. ? 1b0: device mode ? 1b1: host mode host and device 1b0 gintmsk: core interrupt mask register (offset: 0x0 18 ) bits type name description mode initial value 31 r / w wkupintmsk resume/remote wakeup detected i nterrupt mask host and device 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 148 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 21 r / w incomplpmsk incomplete periodic transfer mask incomplete isochronous out transfer mask (incompisooutmsk) host only device only 1b0 20 r / w incompisoin msk incomplete isochronous in transfer mask device only 1b0 19 r / w oepintmsk out endpoints interrupt mask device only 1b0 18 r / w iepintmsk in endpoints interrupt mask device only 1b0 17 r / w epmismsk endpoint mismatch interrupt mask device only 1b0 16 - - reserved 1b0 15 r / w eopfmsk end of periodic frame interrupt mask device only 1b0 14 r / w isooutdrop msk isochronous out packet dropped interrupt mask device only 1b0 13 r / w enumdonem sk enumeration done mask device only 1b0 12 r / w usbrstmsk usb reset mask device o nly 1b0 11 r / w usbsuspmsk usb suspend mask device only 1b0 10 r / w erlysuspmsk early suspend mask device only 1b0 9 r / w i2cintmsk i2c interrupt mask host and device 1b0 8 r / w ulpickintmsk i2cckintmsk ulpi carkit interrupt mask i2c carkit interrup t mask host and device 1b0 7 r / w goutnakeff msk global out nak effec tive mask device only 1b0 6 r / w ginnakeffm sk global non - periodic in nak effec tive mask device only 1b0 5 r / w nptxfempm sk non - periodic txfifo empty mask host and device 1b0 4 r / w rx flvlmsk receive fifo non - empty mask host and device 1b0 3 r / w sofmsk start of (micro)frame mask host and device 1b0 2 r / w otgintmsk otg interrupt mask host and device 1b0 1 r / w modemismsk mode mismatch interrupt mask host and device 1b0 0 - - reser ved - 1b0 grxstsr/grxstsp : rec eive status debug read/status read and pop registers (offset: 0x0 18 ) bits type name description mode initial value 31 :20 reserved resume/remote wakeup detected interrupt mask - 11h0 ? 4b0010: in data packet received ? 4b0011: in transfer completed (triggers an b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 149 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 4b0101: data toggle error (triggers an interrupt) ? 4b0111: channel halted (triggers an interrupt) ? others: reserved 16:15 r / w dpid data pid indicates the data pid of the rec eived packet ? 2b00: data0 ? 2b10: data1 ? 2b01: data2 ? 2b11: mdata - 2b0 14:4 ro bcnt byte count indicates the byte count of the received in data packet. - 11h0 3:0 ro chnum channel num ber indicates the channel number to which the current received packet belongs. - 4h0 grxstsr/grxstsp : device mode receive status debug read/status read and pop registers bits type name description mode initial value 31 :25 - - reserved - 7h0 4h0 ? 4b0001: global out nak (triggers an interrupt) ? 4b0010: out data packet received ? 4b0011: out transfer completed (triggers an ? 4b0100: setup transaction completed (triggers ? 4b0110: setup data ? 4h0 ? 2b00: data0 ? 2b10: data1 ? 2b01: data2 ? 2b11: mdata 2b0 11h0 4h0 16h ? ? free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 150 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years the power - on reset value of this register is specified as the largest rx data fifo depth (parameter otg_ rx_dfifo_depth) during corecons ultant configuration. if enable dynamic fifo sizing? was deselected in coreconsultant (parameter otg_dfifo_dynamic = 0), these flops are optimized, and reads return the power - on value. if enable dynamic fifo sizing? was selected in coreconsultant (paramet er otg_dfifo_dynamic = 1), you can write a new value in this field. you can write a new value in this field. programmed values must not exceed the power - on value set in coreconsultant. gnptxfsiz: non - periodic transmit fifo size register (offset: 0x0 28 ) bits type name description mode initial value 31 :16 ro/r _w nptxfdep non - periodic txfifo depth for host mode, this field is always valid. for device mode, this field is valid only when otg_en_ded_tx_fifo = 0 this value is in terms of 32 - bi t words. minimum value is 16 maximum value is 32,768 the power - on reset value of this register is specified as the largest non - periodic tx data fifo depth (parameter otg_tx_nperio_dfifo_depth when otg_en_ded_tx_fifo = 0. parameter otg_tx_hnperio_dfifo_dep th when otg_en_ded_tx_fifo = 1) during coreconsultant configuration. if enable dynamic fifo sizing? was deselected in coreconsultant (parameter otg_dfifo_dynamic = 0), these flops are optimized, and reads return the power - on value. if enable dynamic fif o sizing? was selected in coreconsultant (parameter otg_dfifo_dynamic = 1), you can write a new value in this field. programmed values must not exceed the power - on value set in coreconsultant. in endpoint txfifo 0 depth (ineptxf0dep) this field is valid on ly for device mode and when otg_en_ded_tx_fifo = 1 this value is in terms of 32 - bit words. minimum value is 16 maximum value is 32,768 the power - on reset value of this register is specified as the largest in endpoint fifo 0 depth (parameter otg_tx_dinep_ dfifo_depth_0) during coreconsultant configuration. if enable dynamic fifo sizing? was deselected in coreconsultant (parameter otg_dfifo_dynamic = 0), these flops are optimized, and reads return the power - on value. if enable dynamic fifo sizing? was selec ted in coreconsultant (parameter otg_dfifo_dynamic = - user - selected free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 151 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1), you can write a new value in this field. programmed values must not exceed the power - on value set in coreconsultant. 15:0 ro/r _w nptxfstaddr non - periodic transmit ram start address for host mode, this field is always valid. for device mode, this field is valid only when otg_en_ded_tx_fifo = 0 this field contains the memory start address for non - periodic transmit fifo ram. the power - on reset value of this register is specified as th e largest rx data fifo depth (parameter otg_rx_dfifo_depth) during coreconsultant configuration. if enable dynamic fifo sizing? was deselected in coreconsultant (parameter otg_dfifo_dynamic = 0), these flops are optimized, and reads return the power - on v alue. if enable dynamic fifo sizing? was selected in coreconsultant (parameter otg_dfifo_dynamic = 1), you can write a new value in this field. programmed values must not exceed the power - on value set in coreconsultant. in endpoint fifo0 transmit ram start address (ineptxf0staddr) this field is valid only for device mode and when otg_en_ded_tx_fifo = 1 this field contains the memory start address for in endpoint transmit fifo# 0. the power - on reset value of this register is specified as the largest rx dat a fifo depth (parameter otg_rx_dfifo_depth) during coreconsultant configuration. otg_rx_dfifo_depth if enable dynamic fifo sizing? was deselected in coreconsultant (parameter otg_dfifo_dynamic = 0), these flops are optimized, and reads return the power - on value. if enable dynamic fifo sizing? was selected in coreconsultant (parameter otg_dfifo_dynamic = 1), you can write a new value in this field. programmed values must not exceed the power - on value set in coreconsultant. - user - selected gnptxsts: non - periodic transmit fifo/queue status register (offset: 0x0 2c ) bits type name description mode initial value 31 ro - reserved - 1b0 ? ? 2b00: in/out token 2b01: zero 7h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 152 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years in/host out) - 2b10: ping/csplit token - 2b11: channel halt command ? bit [24]: terminate (last e ntry for selected channel/endpoint) 23:16 ro nptxqspcav ail non - periodic transmit request queue space available indicates the amount of free space available in the non - periodic transmit request queue. this queue holds both in and out requests in h ost mode. device mode has only in requests. ? 8h0: non - periodic transmit request queue is full ? 8h1: 1 location available ? 8h2: 2 locations available ? n: n locations availab le (0 n 8) ? others: reserved - user - selected 15:0 ro nptxfspcav ail non - periodic txfifo space avail indicates the amount of free space available in the non - periodic txfifo. values are in terms of 32 - bit words. ? 16h0: non - periodic txfifo is full ? 1 6h1: 1 word available ? 16h2: 2 words available ? 16hn: n words available (where 0 n 32,768) ? 16h8000: 32,768 words available ? others: reserved - user - selected gi2cctl:i2c access register ( offset: 0x0 30 ) bits type name description mode initial value 31 r _ ws _ sc bsydne i2c busy/done the application sets this bit to 1b1 to start a request the core deasserts this bit to 1b0. as long as the bit 1b0 ? 1b1: read ? 1b0: write 1b0 1b0 ? 2b00: 7h2c ? 2b01: 7h2d ? 2b10: 7h2e ? 2b11: 7h2f 1b 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 153 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years selects the address of the i c slave on the usb 1.1 full - speed serial transceiver that the core uses for otg signaling. ? 2b00: 7h2c ? 2b01: 7h2d ? 2b10: 7h2e ? 2b11: 7h2f 25 r/w i2csuspct l i2c suspend control selects how suspend is connected to a full - speed transceiver in i2c mode. 1b0: use the dedicated utmi_suspend_n pin 1b1: use an i2c write to program the suspend bit in the phy register - 1b0 24 ro ack i2c ack indicates whether an ack response was received from the i 2 c slave. this bit is valid when bsydne is cleared by the core, after application has initiated an i2c access. ? 1b0: nak ? 1b1: ack - 1b1 23 r/w i2cen i2c enable enables the i2c master to initiate i2c transactions on the i2c interface. - 1b0 22:16 r/w addr i2c address this is the 7 - bit i2c device address used by software to access any external i2c slave, including the i2c slave on a usb 1.1 otg full - speed serial transceiver. software can change this address to acc ess different i2c slaves. - 7h0 15:8 r/w regaddr i2c register addr this field programs the address of the register to be read from or written to. - 8h00 7:0 r/w rwdata i2c read/write data after a register read operation, this field holds the read data for the application. during a write operation, the application can use this register to program the write data to be written to a register. during writes, this field holds the write data. - 8h00 gpvndctl: phy vendor control register (offset: 0x0 34 ) bit s type name description mode initial value 31 r _ ws _ sc disulpidrvr disable ulpi drivers this field is used only if the carkit interface was enabled in coreconsultant (parameter otg_ulpi_ carkit = 1). otherwise, reads return 0. the application sets this bit when it has finished processing the ulpi carkit interrupt (gintsts. ulpickint). when set, the dwc_otg core disables drivers for output signals and masks input signal for the ulpi interface. dwc_otg clears this bit before enabling the ulpi interface. - 1b 3h0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 154 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years sc is done. this bit is cleared by the core when the application sets the new register request bit (bit 25). 26 ro vstsbsy vstatus busy the core sets this bit when the vendor control access is in progress and clears this bit when done. - 1b0 25 r _ ws _ sc newregreq new register request the application sets this bit for a new vendor control access. - 1b0 24:23 - - reserved - 2h0 2 2 r/w regwr register write set this bit for register writes, and clear it for register reads. - 1b0 21:16 r/w regaddr register address the 6 - bit phy r egister address for immediate phy register set access. set to 6h2f for extended phy register set acce ss. - 6h0 15:8 r/w vctrl utmi+ vendor control register address the 4 - bit register address a vendor defined 4 - bit parallel output bus. bits 11:8 of this field are placed on utmi_vcontrol[3:0]. ulpi extended register address (extregaddr) the 6 - bit phy ext ended r egister address. - 8h0 7:0 r/w regdata register data contains the write data for register write. read data for register read, valid when vstatus done is set. - 8h0 ggpio: general purpose input/output register (offset: 0x0 38 ) bits type name descr iption mode initial value 31 :16 r/w gpo general purpose output this field is driven as an output from the core, gp_o[15:0]. the application can program this field to determine the corresponding value on the gp_o[15:0] output. - 16h0 this fields read value reflects the gp_i*15:0+ core 16h0 32h4f54 ? 2b00: bidir (in and out) endpoint free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 155 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 2b01: in endpoint ? 2b10: out endpoint ? 2b11: reserved bits [31:30]: endpoint 15 direct ion bits [29:28]: endpoint 14 direction ... bits [3:2]: endpoint 1 direction bits[1:0]: endpoint 0 direction (always bidir) (coreconsultant parameter: otg_ep_dir_n). ghwcfg2 : user hw config2 register (offset: 0x0 48 ) bits type name descri ption mode initial value 31 - - reserved - 1b0 C ? 2b00: 2 ? 2b01: 4 ? 2b10: 8 ? ? 2b00: 2 ? 2b01: 4 ? 2b10: 8 ? 2b0 ? 1b0: no ? 1b1: yes ? 1b0: no ? 1b1: yes C C free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 156 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 9:8 ro fsphytype full - speed phy interface type ? 2b00: full - speed interface not supported ? 2b01: dedicated full - speed interface ? 2b10: fs pin s shared with utmi+ pins ? 2b11: fs pins shared with ulpi pins (coreconsultant parameter: otg_fsphy_ interface) - user - selected 7:6 ro hsphytype high - speed phy interface type ? 2b00: high - speed interface not supported ? 2b01: utmi+ ? 2b10: ulpi ? 2 b11: utmi+ and ulpi (coreconsultant parameter: otg_hsphy_ interface) - user - selected 5 ro singpnt point - to - point ? 1b0: multi - point application ? 1b1: single - point application (coreconsultant parameter: otg_single_ point) - user - selected 4:3 ro otgar ch architecture ? 2b00: slave - only ? 2b01: external dma ? 2b10: internal dma ? others: reserved (coreconsultant parameter:otg_ architecture ) - user - selected 2:0 ro otgmode mode of operation ? 3b000: hnp - and srp - capable otg (host & device) ? 3b001: srp - capable otg (host & device) ? 3b010: non - hnp and non - srp capable otg (host &device) ? 3b011: srp - capable device ? 3b100: non - otg device ? 3b101: srp - capable host ? 3b110: non - otg host ? others: reserved (coreconsultant parameter: otg_mode ) - user - selected ghwcfg3 : user hw config3 register (offset: 0x0 4c ) bits type name description mode initial value 31 :16 ro dfifodepth dfifo depth this value is in terms of 32 - bit words. ? ? 4b0 ? 1b0: asynchronous reset is used in the core ? 1b1: synchronous reset is used in the core free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 157 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years interface ports, and sof toggle and counter ports were removed for gate count optimization by enabling remove optional features? during corecon sultant configuration. ? 1b0: no ? 1b1: yes (coreconsultant parameter: otg_rm_opt_features) 9 ro vndctlsupt vendor control interface support ? 1b0: vendor control interface is not available on the core. ? 1b1: vendor control interfac e is available. (coreconsultant parameter: otg_vendor_ctl_ interface) - user - selected 8 ro i2cintsel i2c selection ? 1b0: i2c interface is not available on the core. ? 1b1: i2c interface is available on the core. (coreconsultant parameter: otg_i2c_ in terface) - user - selected 7 ro otgen otg function enabled the application uses this bit to indicate the dwc_otg cores otg capabilities. ? 1b0: not otg capable ? 1b1: otg capable (coreconsultant parameter: otg_mode) - 1b1 6:4 ro pktsizewidth width of transfer size counters ? 4b0000: 11 bits ? 4b0001: 12 bits ... ? 4b1000: 19 bits ? others: reserved (coreconsultant parameter: otg_trans_ count_width) - user - selected 3:0 ro xfersizewidth width of transfer size counters ? 4b0000: 11 bits ? 4b0001: 12 bits ... ? 4b1000: 19 bits ? others: reserved (coreconsultant parameter: otg_trans_ count_width) - user - selected ghwcfg4 : user hw config4 register (offset: 0x0 50 ) bits type name description mode initial value 31 :30 - - reserved - 2h0 ? ? ? free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 158 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 15 : 16 in endpoints 25 ro dedfifomode enable dedicated transmit fifo for device in endpoints ? 1b0 : dedicat ed transmit fifo operation not enabled. ? 1b1 : dedicated transmit fifo operation enabled. (coreconsultant parameter : otg_en_ded_ tx_fifo) - user selected 24 ro sessendfltr session_end filter enabled ? 1b0: no filter ? 1b1: filter (coreconsultant parameter: otg_en_ sessionend_filter) - user - selected 23 ro bvalidfltr b_valid filter enabled ? 1b0: no filter ? 1b1: filter (coreconsultant parameter: otg_en_b_valid_ filter) - user - selected 22 ro avalidfltr a_valid filter enabled ? 1b0: no filter ? 1b1: filter (coreconsultant parameter: otg_en_a_valid_ filter) - user - selected 21 ro vbusvalidfltr vbus_valid filter enabled ? 1b0: no filter ? 1b1: filter (coreconsultant parameter: otg_en_ vbusvalid_filter) - user - selected 20 ro iddgf ltr iddig filter enable ? 1b0: no filter ? 1b1: filter (coreconsultant parameter: otg_en_iddig_ filter) - user - selected 19:16 ro numctleps number of device mode control endpoints in addition to endpoint 0 range: 0 - 15 (coreconsultant parameter: otg_n um_crl_ eps) - user - selected 15:14 ro phydatawidth utmi+ phy/ulpi - to - internal utmi+ wrapper data width when a ulpi phy is used, an internal wrapper converts ulpi to utmi+ . ? 2b00: 8 bits ? 2b01: 16 bits ? 2b10: 8/16 bits, software selectable ? othe rs: reserved (coreconsultant parameter: otg_hsphy_ dwidth) - user - selected 13:6 - - reserved - 8h0 5 ro ahbfreq minimum ahb fr equency less than 60 mhz - user - free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 159 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 1b0: no ? 1b1: yes (coreconsultant parameter:otg_min_ahb _ freq _lessthan_60) selected 4 ro enablepwropt enable power optimization? ? 1b0: no ? 1b1: yes (coreconsultant parameter: otg_en_pwropt) - user - selected 3:0 ro numdevperioeps number of device mode periodic in endpoints range: 0 C 15 (coreconsultant parameter: otg_num_ perio _ eps) user - selected hptxfsiz: host periodic transmit fifo size register (offset: 0x 100 ) bits type name description mode initial value 31:16 ro / r_w ptxfsize host periodic txfifo depth this value is in terms of 32 - bit words. ? ? ? ? free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 160 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years programmed values must not exceed the power - on value set in coreconsultant. dptxfsizn: device periodic transmit fifo - n size register fifo_number : 1 n 15 , ( offset: 104h + (fifo_number - 1) * 04hh ) bits type name description mode initial value 31:16 ro dptxfsize device periodic txfifo size this value is in terms of 32 - bit words. ? ? ? ? fifo_number : 1 n 15 ( offset: 104h + (fifo_number ? 1) * 04h ) bits type name description mode initial value 31:16 ro / r_w inepntxfdep in endpoint txfifo depth this value is in terms of 32 - bit words. minimum value is 16 maximum value is 32 ,768 the power - on reset value of this register is specified as the largest in endpoint fifo number depth (parameter otg_tx_dinep_ dfifo_depth_n) during coreconsultant configuration (0 RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 161 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years reads return the power - on value. if enable dynamic fifo sizing? was selected in coreconsultant (parameter otg_dfifo_dynamic = 1), you can write a new value in this field. programmed valu es must not exceed the power - on value set in coreconsultant. 15:0 ro / r_w inepntxfstaddr in endpoint fifon transmit ram start address this field contains the memory start address for in endpoint transmit fifon (0 RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 162 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 15:0 ro / r_w inepntxfstadd r in endpoint fifon transmit ram start address this field contains the memory start address for in endpoint transmit fifon (0 RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 163 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ls mode. ? 2b10: phy clock is running at 6 mhz. in usb 1.1 fs mode, use 6 mhz when the utmi+ phy low power mode is selected and the phy supplies a 6 mhz clock during ls mode. if you select a 6 mhz clock during ls mode, you must do a soft r eset. ? 2b11: reserved hfir: host frame interval register (offset: 0x 404 ) bits type name description mode initial value 31:16 - - reserved - 16h0 ? 125 s * (phy clock frequency for hs) ? 1 ms * (phy clock frequency for fs/ls) 16d60000 16h0 reaches 16h3fff. 16h3fff 8h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 164 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years request queue tcurrently being processes by the mac. this register is used for debugging. ? bit [31]: odd/even (micro)frame - 1b0: send in even (micro)frame - 1b1: send in odd (micro)frame ? bits [30:27]: channel /endpoint number ? bits [26:25]: type - 2b00: in/out - 2b01: zero - length packet - 2b10: csplit - 2b11: disable channel command ? bit [24]: terminate (last entry for the selected channel/endpoint). 23:16 ro ptxqspcavail periodic transmit reques t queue space available indicates the number of free locations available to be written in the periodic transmit request queue. this queue holds both in and out requests. ? 8h0: periodic transmit request queue is full ? 8h1: 1 location available ? 8h2: 2 locations available ? n: n locations available (0 n 8) ? others: reserved - user selected 15:0 r/w ptxfspcavail periodic transmit data fifo space available indicates the number of free locations available to be written to in the periodic txfifo. va lues are in terms of 32 - bit words ? 16h0: periodic txfifo is full ? 16h1: 1 word available ? 16h2: 2 words available ? 16hn: n words available (where 0 n 32,768) ? 16h8000: 32,768 words available ? others: reserved - user selected haint: host al l channels interrupt register (offset: 0x 414 ) bits type name description mode initial value 31:16 - - reserved - 16h0 16h0 12h0 ? 2b00: high speed ? 2b01: full speed ? 2b10: low speed 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 165 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 2 b11: reserved 16:13 r/w prttstctl port test control the application writes a nonzero value to this field to put the port into a test mode, and the corresponding pattern is signaled on the port. ? 4b0000: test mode disabled ? 4b0001: test_j mode ? 4b0010: test_k mode ? 4b0011: test_se0 _nak mode ? 4b0100: test_packet mode ? 4b0101: test_force_enable ? others: reserved - 4h0 12 r _ w _ sc prtpwr port power the application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. ? 1b0: power off ? 1b1: power on - 1b0 11:10 ro prtlnsts port line status indicates the current logic level usb data lines ? bit [10]: logic level of d+ ? bit [11]: logic level of d C - 2b0 9 - - reserved - 1b0 8 r/w prt rst port reset when the application sets this bit, a reset sequence is started on this port. the application must time the reset period and clear this bit after the reset sequence is complete. ? 1b0: port not in reset ? 1b1: port in reset the applicatio n must leave this bit set for at least a minimum duration mentioned below to start a reset on the port. the application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maxim um limit set by the usb standard. ? high speed: 50 ms ? full speed/low speed: 10 ms - 1b0 7 r _ ws _ sc prtsusp port suspend the application sets this bit to put this port in suspend mode. the core only stops sending sofs when this is set. to stop the phy c lock, the application must set the port clock stop bit, which asserts the suspend input pin of the phy. the read value of this bit reflects the current suspend status of the port. this bit is cleared by the core after a remote wakeup signal is detected or the application sets the port reset bit or port resume bit in this register or the - 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 166 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years resume/remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (gintsts.wkupint or gintsts.disconnint, respectively). ? 1b 0: port not in suspend mode ? 1b1: port in suspend mode 6 r _ w _ ss _ sc prtres port resume the application sets this bit to drive resume signaling on the port. the core continues to drive the resume signal until the application clears this bit. if the core detects a usb remote wakeup sequence, as indicated by the port resume/remote wakeup detected interrupt bit of the cor e interrupt register(gintsts.wkupint), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. the read value of this bit indicates whether the core is currently driving resume signaling. ? 1b0: no r esume driven ? 1b1: resume driven - 1b0 5 r _ ss _ wc prtovrcurrchng port overcurrent change the core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. - 1b0 4 ro prtovrcurract port overcurrent active indicates the overcurrent condition of the port. ? 1b0: no overcurrent condition ? 1b1: overcurrent condition - 1 b0 3 r _ ss _ wc prtenchng port enable/disable change the core sets this bit when the status of the port enable bit [2] of this register changes. - 1b0 2 r _ ss _ sc _ w c prtena port enable a port is enabled only by the core after a reset sequence, and is disabl ed by an overcurrent condition, a disconnect condition, or by the application clearing this bit. the application cannot set this bit by a register write. it can only clear it to disable the port. this bit does not trigger any interrupt to the application. ? 1b0: port disabled ? 1b1: port enabled - 1b0 1 r _ ss _ wc prtconndet port connect detected the core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit of the cor e interrupt reg ister (gintsts.prtint). the application must write a 1 to this bit to clear the interrupt. - 1b0 0 ro prtconnsts port connect status ? 0: no device is attached to the por t. ? 1: a device is attached to the por t. 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 167 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years hccharn: host channel - n characteri stics register channel_number: 0 n 15 ( offset: 500h + (channel_number * 20h) ) bits type name description mode initial value 31 r _ ws _ sc chena channel enable this field is set by the application and cleared by the otg host ? 1b0: channel disabled ? 1b 1b0 1b0 ? 1b0: even (micro)frame ? 1b1: odd (micro)frame 1b0 7h0 ec multi count / / error count when the spl it enable bit of the host channel - n split control register (hcspltn.spltena) is reset (1b0), this field indicates to the host the number ? 2b00: reserved this field yields undefined ? 2b01: 1 transaction ? 2b10: 2 transactions to be iss ? 2b11: 3 transactions to be issued for this when hcsp ltn.spltena is set (1b1), this field least 2b01. 2b0 ? 2b00: control 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 168 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 2b01: isochronous ? 2b10: bulk ? 2b11: interrupt 17 r/w lspddev low - speed device this field i s set by the application to indicate that this channel is communicating to a low - speed device. - 1b0 16 - - reserved - 1b0 15 r/w epdir endpoint direction indicates whether the transaction is in or out. ? 1b0: out ? 1b1: in - 1b0 14:11 r/w epnum en dpoint number indicates the endpoint number on the device serving as the data source or sink. - 4h0 10:0 r/w mps maximum packet size indicates the maximum packet size of the associated endpoint. - 11h0 hcspltn: host channel - n split control register cha nnel_number: 0 n 15 ( offset: 504h + (channel_number * 20h) ) bits type name description mode initial value 31 r / w spltena split enable the application sets this field to indicate that this channel is enabled to perform split transactions. - 1b0 14h0 1b0 ? 2b11: all. this is the entire data payload is of ? 2b10: begin. this is the first data payload of ? 2b00: mid. this is the middle payload of this ? 2b01: end. this is the last payload of this 2h0 translators hub. 7h0 7h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 169 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years hcintn: host channel - n interrupt register channel_number: 0 n 15 ( offset: 508h + (channel_number * 20h) ) bits type name description mode initial value 31:11 - - reserved - 21h0 1b0 1b0 1b0 ? crc check failure ? timeout ? bit stuff error ?false eop 1b0 1b0 1b0 1b0 1b0 corresponding channels dma address register 1b0 1b0 1b0 channel_number: 0 n 15 ( offset: 50ch + (channel_number * 20h) ) bits type name description mode initial value 31:11 - - reserved - 21h0 1b0 1b0 1b0 1b0 1b0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 170 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 4 r/w nakmsk nak response received interrupt mask - 1b0 3 r/w stallmsk stall response rec eived interrupt mask - 1b0 2 r/w ahberrmsk ahb error mask - 1b0 1 r/w chhltdmsk channel halted mask - 1b0 0 r/w xfercomplmsk transfer completed mask - 1b0 hctsizn: host channel - n interrupt mask register chann el_number: 0 n 15 ( offset: 510h + (channel_number * 20h) ) bits type name description mode initial value 31 r/w dopng setting this field to 1 directs the host to do ping protocol - 1h0 ? 2b00: data0 ? 2b01: data2 ? 2b10: data1 ? 2b11: mdata (non 2b0 10b0 19b0 channel_number: 0 n 1 5 ( offset: 514h + (channel_number * 20h) ) bits type name description mode initial value 31 :0 r/w dmaaddr dma address this field holds the start address in the external memory from which the data for the endpoint - 32h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 171 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years must be fetched or to which it must be stor ed. this register is incremented on every ahb transaction. dcfg : device configuration register (offset: 0x 800 ) bits type name description mode initial value 31:23 - - reserved - 9h0 5h8 5h0 ? 2b00: 80% of the (micro)frame interval ? 2b01: 85% ? 2b10: 90% ? 2b 2h0 7h0 1b0 transaction of a control transfers status stage. ? 1b1: send a stall handshake on a nonzero ? 1b0: send the rec eived out packet to the 1b0 the core is connected. see device initialization 2b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 172 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? 2b00: high speed (usb 2.0 phy clock is 30 mhz or 60 mhz) ? 2b01: full speed (usb 2.0 phy clock is 30 mhz or 60 mhz) ? 2b10: low speed (u sb 1.1 transceiver clock is 6 mhz). if you select 6 mhz ls mode, you must do a soft reset . ? 2b11: full speed (usb 1.1 transceiver clock is 48 mhz) dctl : device control register (offset: 0x 804 ) bits type name description mode initial value 31:12 - - reserved - 20h0 information, see device mode suspend and down on page 422. 1b0 1b0 1b0 1b0 1b0 ? 3b000: test mode disabled ? 3b001: test_j mode ? 3b010: test_k mode ? 3b011: test_se0_nak mode ? 3b100: test_packet mode ? 3b101: test_force_enable ? others: reserved 3b0 ? 1b0: a handshake is sent based on the fifo 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 173 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years status and the nak and stall bit settings. ? 1b1: no data is written to the rxfifo, irrespective of space availability. sends a nak handshake on all packets, except on setup transactions. all isochronous out packets are dropped. 2 ro gnpinnaksts global non - periodic in nak status ? 1'b0: a handshake is sent out based on the data availability in the transmit fifo. ? 1'b1: a nak handshake is sent out on all n on - periodic in endpoints, irrespective of the data availability in the transmit fifo. - 1b0 1 r/w sftdiscon soft disconnect the application uses this bit to signal the dwc_otg core to do a soft disconnect. as long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the usb. the core stays in the disconnected state until the application clears this bit. the minimum duration for which the core must keep this bit set is specified in table 5 - 45 . ? 1b0: normal operation. when this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the utmi+ to 2b00, which generates a device connect event to the usb host. when the device is reconnected, the usb host restart s device enumeration. ? 1b1: the core drives the phy_opmode_o signal on the utmi+ to 2b01, which generates a device disconnect event to the usb host. - 1b0 0 r/w rmtwkupsig remote wakeup signaling when the application sets this bit, the core init iates remote signaling to wake up the usb host. the application must set this bit to instruct the core to exit the suspend state. as specified in the usb 2.0 specification, the application must clear this bit 1 C 15 ms after setting it. - 1b0 dsts : device status register ( offset: 0x808) bits type name description mode initial value 31:22 - - reserved - 10h0 14h0 4h0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 174 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years (phy_rxvalid_i/ phy_rxvldh_i or phy_rxactive_i is asserted for at least 2 ms, due to phy error) seen on the utmi+ . due to erratic errors, the dwc_otg core goes into suspended state and an interrupt is generated to the application with early suspend bit of the core interrupt register (gintsts.erlysusp). if the ea rly suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover 2:1 ro enumspd enumerated speed indicates the speed at which the dwc_otg core has come up after speed detection through a chirp sequence. ? 2b00: high speed (phy clock is running at 30 or 60 mhz) ? 2b01: full speed (phy clock is running at 30 or 60 mhz) ? 2b10: low speed (phy clock is running at 6 mhz) ? 2b11: full speed (phy clock is running at 48 mhz) low speed is not supporte d for devices using a utmi+ phy. - 2h01 0 ro suspsts suspend status in device mode, this bit is set as long as a suspend condition is detected on the usb. the core enters the suspended state when there is no activity on the phy_line_state_i signal for a n extended period of time. the core comes out of the suspend: ? when ther e is any activity on the phy_line_state_i signal ? when the application writes to the remote wakeup signaling bit in the device control register (dctl.rmtwkupsig). - 1b0 diepmsk : device in endpoint common interrupt mask register ( offset: 0x810) bits type name description mode initial value 31:9 - - reserved - 23h0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 23h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 175 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 8 r/w outpkterrmsk out packet error mask - 1b0 7 - - reserved - 1b0 6 r/w back2backsetup back - to - back setup packets received mask applies to control out endpoints only. - 1b0 5 - - reserved - 1b0 4 r/w outtknepdismsk out token received when endpoint disabled mask applies to control out endpoints only. - 1b0 3 r/w setupmsk setup phase done mask applies to control endpoints only. - 1b0 2 r/w ahberrmsk ahb error - 1b0 1 r/w epdisbldmsk endpoint d isabled interrupt mask - 1b0 0 r/w xfercomplmsk transfer completed interrupt mask - 1b0 daint: device all endpoints interrupt register ( offset: 0x818) bits type name description mode initial value 31:16 ro outepint out endpoint interrupt bits one bit per out endpoint: bit 16 for out endpoint 0, bit 31 for out endpoint 15 - 16h0 16h0 16h0 16h0 ? bits *31:28+: endpoint number of token 5 ? bits *27:24+: endpoint number of token 4 ? bits *15:12+: endpoint number of token 1 ? bits *11:8+: endpoint number of token 0 24h0 1b0 2h0 5h0 ? bits *31:28+: endpoint number of token 13 ? bits *27:24+: endpoint number of token 12 32h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 176 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ....... ? bits *7:4+: endpoint number of token 7 ? bits *3:0+: endpoint number of token 6 dtknqr 3 :device in token sequence learning queue register 3 ( offset: 0x0830) bits type name description mode initial value 31:0 ro eptkn endpoint token four bits per token represent the endpoint number of the token: ? bits *31:28+: endpoint number of token 21 ? bits *27:24+: endpoint number of token 20 ? bits *7:4+: endpoint number of token 15 ? bits *3:0+: endpoint number of token 14 32h0 ? bits *31:28+: endpoint number of token 29 ? bits *27:24+: endpoint number of token 2 ? bits *7:4+: endpoint number of token 23 ? bits *3:0+: endpoint number of token 22 32h0 16h0 16h0b8f 16h17d7 h0 12h2c6 12h5b8 1b1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 177 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years this bit is set to one, then the arbiter parks on the in endpoint for which there is a token received on the usb. this is done to avoid getting into underrun conditions. by default the park ing is enabled. 26 - - reserved - 1b1 25:17 r/w rxthrlen receive thr eshold length this field specifies receive thresholding size in dwords. this field also specifies the amount of data received on the usb befor e the core can start transmitting o n the ahb. the threshold length has to be at least eight dwords. the recommended value for thrlen is to be the same as the programmed ahb burst length (gahbcfg.hbstlen). - 9h8 16 r/w rxthren receive thr eshold enable when this bit is set, the core enab les thresholding in the receive direction. - 1b0 15:11 - - reserved - 5'b0 10:2 r/w txthrlen transmit threshold length this field specifies transmit thresholding size in dwords. this field specifies the amount of data in bytes to be in the correspondi ng endpoint transmit fifo, before the core can start transmit on the usb. the threshold length has to be at least eight dwords. this field controls both isochronous and non - isochronous in endpoint thresholds. the recommended value for thrlen is to be the same as the programmed ahb burst length (gahbcfg.hbstlen). - 9h8 1 r/w isothren iso in endpoints threshold enable. when this bit is set, the core enables thresholding for isochronous in endpoints. - 1b0 0 r/w nonisothren non - iso in endpoints threshol d enable. when this bit is set, the core enables thresholding for non isochronous in endpoints. - 1b0 diepempmsk : device in endpoint fifo empty interrupt mask register (offset: 0x 834 ) bits type name description mode initial value 31:16 ro - reserved - 16h0 16h0 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 178 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years endpoint: ? endpoint disabled ? transfer completed 30 r/ws /sc epdis endpoint disable the application sets this bit to stop transmitting data on an endpoint, even befor e the transfer for that endpoint is complete. the application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. - 1b0 29:28 - - reserved - 2 b0 27 wo snak set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for an endpoint after a setup packet is received on that endpoint. - 1b0 26 wo cnak clear nak a write to this bit clears the nak bit for the endpoint. - 1b0 25:22 r/w txfnum txfifo number ? for shared fifo operation, this value is always set to 0, indicating that control in endpoint 0 data is alwa ys written in the non - periodic transmit fifo. ? for dedicated fifo operation, this value is set to the fifo number that is assigned to in endpoint 0. - 4h0 21 r/ws /sc stall stall handshake the application can only set this bit, and the core clears i t, when a setup token is received for this endpoint. if a nak bit, global non - periodic in nak, or global out nak is set along with this bit, the stall bit takes priority. - 1b0 20 - - reserved - 1b0 19:18 ro eptype endpoint type hardcoded to 00 for co ntrol. - 2h0 17 ro naksts nak status indicates the following: ? 1b0: the core is transmitting non - nak handshakes based on the fifo status ? 1b1: the core is transmitting nak handshakes on this endpoint. when this bit is set, either by the applica tion or core, the core stops transmitting data, even if there is data available in the txfifo. irrespective of this bits setting, the core always responds to setup data packets with an ack handshake. - 1b0 16 - - reserved - 1b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 179 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 15 ro usbactep usb acti ve endpoint this bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. - 1b1 14:11 r/w nextep next endpoint applies to non - periodic in endpoints only. indicates the endpoint number to be fetch ed after the data for the current endpoint is fetched. the core can access this field, even when the endpoint enable (epena) bit is not set. this field is not valid in slave mode. note : this field is valid only for shared fifo operations. - 4b0 10:2 - - reserved - 9h0 1:0 r/w mps maximum packet size applies to in and out endpoints. the application must program this field with the maximum packet size for the current logical endpoint. ? 2b00: 64 bytes ? 2b01: 32 bytes ? 2b10: 16 bytes ? 2b11: 8 bytes - 2h0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 180 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20 802.11n 2t2r mac/bbp 3.20.1 features ? 1x1/1x2/2x1/2x2 modes. ? 300mhz phy rate support. ? legacy and high throughput modes. ? 20mhz/40mhz bandwidth. ? reverse direction data flow and frame aggr egation ? wep 64/128, wpa, wpa2 support ? qos C wmm, wmm - ps ? wake on wireless lan ? multiple bssid support ? international regulation - 802.11d +h ? cisco ccx v1.0 v2.0 v3.0 compliance ? bluetooth co - existence ? low power with advanced power management 3.20.2 block diagram fig. 3 - 20 - 1 802. 11n 2t2r mac/bbp block diagram w p d m a s e c p b f m a c b b p / a d c / d a c w m m s c h r b u s p a l m b u s c s r p a c k e t b u f f e r s e c t a b l e s free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 181 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years fig. 3 - 20 - 2 802.11n 2t2r mac/bbp register map 3.20.3 register description (base: 0x1018.0000) 3.20.3.1 register description - sch/wpdma (base: 1018.0000) int_status: int_status register (offset: 0x0200) bits t ype name description initial value 31:21 - - reserved 0 20 r/w radar_int bbp radar detection interrupt 0 19:18 - - reserved 0 17 r/w tx_coherent tx_dma finds data coherent event when checking ddone bit. write 1 to clear the interrupt. read to get the r aw interrupt status 0 16 r/w rx_coherent rx_dma finds data coherent event when checking ddone bit. write 1 to clear the interrupt. 0 mac search table(800h) program memory (2000h) mac register (800h) reserved(200h) cis (100h) beacon frame (800h) null frame (100h) distributed re gist er sram (8kb) sch/ wp dma register (200h) 0200 h 0400 h 1000 h 1800 h 2000 h 0000 h packet buffer (8000 h) 8000 h sys/pbf/fce/misc register (400h) fce table (1000h) 4000 h mac key table (2600h) sram (32kb) sram (16kb) 0800 h reserved ( 800h) sram (2kb) free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 182 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years read to get the raw interrupt status 15 r/w mac_int_4 mac interrupt 4 : gp timer interrupt 0 14 r/w mac_int_3 mac interru pt 3 : auto wakeup interrupt 0 13 r/w mac_int_2 mac interrupt 2 : tx status interrupt 0 12 r/w mac_int_1 mac interrupt 1 : pre - tbtt interrupt 0 11 r/w mac_int_0 mac interrupt 0 : tbtt interrupt 0 10 ro tx_rx_cohere nt when tx_coherent or rx_coherent is on, this bit is set 0 9 r/w mcu_cmd_int mcu command interrupt 0 8 r/w tx_do ne_int5 tx queue#5 packet transmit interrupt write 1 to clear the interrupt. 0 7 r/w tx_do ne_int4 tx queue#4 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 6 r/w tx_do ne_int3 tx queue#3 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 5 r/w tx_do ne_int2 tx queue#2 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 4 r/w tx_do ne_int1 tx queue#1 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 3 r/w tx_do ne_int0 tx queue#0 packet transmit interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 2 r/w rx_done_int rx packet receive interrupt write 1 to clear the interrupt. read to get the raw interrupt status 0 1 r/w tx_dly_int summary of the whole wpdma tx related interrupts write 1 to clear the interrupt. read to get the raw interrupt status 0 0 r/w rx_dly_int summary of the whole wpdma rx r elated interrupts write 1 to clear the interrupt. read to get the raw interrupt status 0 int_mask: int_mask register (offset: 0x0204) bits type name description initial value 31:18 - - reserved 0 20 r/w radar_int_en enable for bbp radar detection interrupt 1: enable the interrupt 0: disable the interrupt 0 19:18 - - reserved 0 17 r/w tx_coherent_ en enable for tx_dma data coherent interrupt 1: enable the interrupt 0: disable the in terrupt 0 16 r/w rx_coherent_ en enable for rx_dma data coherent interrupt 1: enable the interrupt 0: disable the interrupt 0 14 r/w mac_int4 _en mac interrupt 4 : gp timer interrupt 0 14 r/w mac_int3 _en mac interrupt 3 : auto wakeup interrupt 0 13 r/w mac _int2 _en mac interrupt 2 : tx status interrupt 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 183 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 12 r/w mac_int1 _en mac interrupt 1 : pre - tbtt interrupt 0 11 r/w mac_int0 _en mac interrupt 0 : tbtt interrupt 0 10 - - reserved 0 9 r/w mcu_cmd_int_ msk mcu command interrupt enable 1 : enable the interrupt 0 : disable the interrupt 0 8 r/w tx_do ne_int_ msk5 tx queue#5 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 7 r/w tx_do ne_int_ msk4 tx queue#4 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 6 r/w tx_do ne_int_ msk 3 tx queue#3 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 5 r/w tx_do ne_int_ msk 2 tx queue#2 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 4 r/w tx_do ne_int_ msk 1 t x queue#1 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 3 r/w tx_do ne_int_ msk 0 tx queue#0 packet transmit interrupt 1 : enable the interrupt 0 : disable the interrupt 0 2 r/w rx_done_int_ msk rx packet receive interrupt 1 : enable the interrupt 0 : disable the interrupt 0 1 r/w tx_dly_int_ msk summary of the whole wpdma tx related interrupts 1 : enable the interrupt 0 : disable the interrupt 0 0 r/w rx_ dly_int_ msk summary of the whole wpdma rx r elated interrupts 1 : en able the interrupt 0 : disable the interrupt 0 wpdma_glo_cfg: wpdma_glo _cfg register (offset: 0x0208) bits type name description initial value 31:16 - - reserved 0 15:8 hdr_seg_len specify the header segment size in byte to support rx header/payload sc attering function, when set to a non - zero value. when set to zero, the header/payload scattering feature is disabled. 8b0 convert payload and tx/rx information. dma wont apply 1b1 2d2 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 184 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3 ro rx_dma_busy 1 : rx_dma is busy 0 : rx_dma is not busy 0 2 r/w rx_dma_en 1 : enable rx_dma 0 : disable rx_dma (when disabled, rx_dma will finish the current rece iving packet, then stop.) 0 1 ro tx_dma_busy 1 : tx_dma is busy 0 : tx_dma is not busy 0 0 r/w tx_dma_en 1 : enable tx_dma 0 : disable tx_dma (when disabled, tx_dma will finish the current sending packet, then stop.) 0 wpdma_rst_idx: wpdma_rst_idx regi ster (offset: 0x020c) bits type name description initial value 31:17 - - reserved 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1b0 1 set to 0 will disable pend ing interrupt count check 7b0 set to 0 will disable pending interrupt time check 8b0 1b0 set to 0 will disable pending interrupt count check 7b0 set to 0 will disable pending interrup t time check 8b0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 185 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years wmm_aifsn_cfg: wmm_aifsn_cfg register (offset: 0x0214) bits type name description initial value 31:16 - - reserved 16b0 4h0 4h0 4h0 4h0 16b0 4h0 4h0 4h0 4h0 16b0 4h0 4h0 4h0 4h0 16h0 16h0 16h0 16h0 20b0 20b0 bits type name description initial value 31:12 - - reserved 20b0 11:0 ro tx_dtx_idx0 point to the next txd dma wants to use 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 186 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_base_ptr1 (offset:0x0240,default :0x000 00000) tx_max_cnt1 (offset:0x0244,default :0x00000000) tx_ctx_idx1 (offset:0x0248,default :0x00000000) tx_dtx_idx1 (offset:0x024c,default :0x00000000) tx_base_ptr2 (offset:0x0250,default :0x00000000) tx_max_cnt2 (offset:0x0254,default :0x00000000) tx_ctx_ idx2 (offset:0x0258,default :0x00000000) tx_dtx_idx2 (offset:0x025c,default :0x00000000) tx_base_ptr3 (offset:0x0260,default :0x00000000) tx_max_cnt3 (offset:0x0264,default :0x00000000) tx_ctx_idx3 (offset:0x0268,default :0x00000000) tx_dtx_idx3 (offset:0 x026c,default :0x00000000) tx_base_ptr4 (offset:0x0270,default :0x00000000) tx_max_cnt4 (offset:0x0274,default :0x00000000) tx_ctx_idx4 (offset:0x0278,default :0x00000000) tx_dtx_idx4 (offset:0x027c,default :0x00000000) tx_base_ptr5 (offset:0x0280,defaul t :0x00000000) tx_max_cnt5 (offset:0x0284,default :0x00000000) tx_ctx_idx5 (offset:0x0288,default :0x00000000) tx_dtx_idx5 (offset:0x028c,default :0x00000000) rx_base_ptr: rx_base_ptr register (offset: 0x0290) bits type name description initial value 31:0 r/w rx_base_ptr0 point to the base address of rxd ring. it should be a 4 - dword aligned address 0 rx_max_cnt: rx_max_cnt register (offset: 0x0294) bits type name description initial value 31:12 - - reserved 0 11:0 r/w rx_max_cnt0 the maximum number of r xd count in rxd ring #0. 0 rx_calc_idx: rx_calc_idx register (offset: 0x0298) bits type name description initial value 31:12 - - reserved 0 11:0 r/w rx_calc_idx0 point to the next rxd cpu wants to allocate to rxd ring #0. 0 fs _drx_idx: fs _drx_idx re gister (offset: 0x029c) bits type name description initial value 31:12 - - reserved 0 11:0 r/w rx_drx_idx0 point to the next rxd dma wants to use in fds ring#0. it should be a 4 - dword aligned address. 0 us_cyc_cnt: us_cyc_cnt register (offset: 0x02a4) b its type name description initial value 31:25 - - reserved 0 24 r/w test_en test mode enable 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 1 87 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 23:16 r/w test_sel test mode selection 8hf0 15:9 - - reserved 0 8 r/w bt_mode_en blue - tooth mode enable 0 7:0 rw us_cyc_cnt clock cycle count in 1us. its dependent on the system clock rate. for system clock rate = 125mhz, set 8h7d for system clock rate = 133mhz, set 8h85 8h21 3.20.3.2 register description - pbf (base: 1018.0000) sys_ctrl: sys_ctrl register (offset: 0x0400) bits type name description initial v alue 31:17 - - reserved 0 18 - - reserved 0 16 r/w hst_pm_sel host program ram write selection. 0 15 reserved 14 r/w cap_mode packet buffer capture mode. 0: packet buffer in normal mode. 1: packet buffer in bbp capture mode. 0 13 - - reserved 1 1 2 r/w clkselect mac/pbf clock source selection. 0: from pll 1: from 40mhz clock input 0 11 r/w pbf_clken pbf clock enable. 0 10 r/w mac_clk_en mac clock enable. 0 9 r/w dma_clk_en dma clock enable. 0 8 - - reserved 0 7 r/w mcu_ready mcu ready. 8051 wr ites 1 to this bit to inform host internal async interface reset. write 1 to this bit will put async pbf hardware reset. write 1 to this bit will put pbf into mac hardware reset. write 1 to this bit will put mac into dma hardware reset. write 1 to this bit will put dma into 3h7 5h14 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 188 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years enabled but empty. after null0 frame transmitted, txq1 will be disabled. 0: disable 1: enable 14 r/w null1 _mode hcca null1 frame auto mode. in this mode, all tx q (0/1/2) will be disabled after null1 frame transmitted. 0: disable 1: enable 0 13 r/w rx_drop_mode rx drop mode. when set, pbf will drop rx packet before into dma. 0: normal mode 1: drop mode 0 12 r/w tx0q_mode tx0q operation mode. 0: auto mode 1: manu al mode 0 11 r/w tx1q_mode tx1q operation mode. 0: auto mode 1: manual mode 0 10 r/w tx2q_mode tx2q operation mode. 0: auto mode 1: manual mode 0 9 r/w rx0q_mode rx0q operation mode. 0: auto mode 1: manual mode 0 8 r/w hcca_mode hcca auto mode. in this mode, txq1 will be enabled when cf - poll arriving. 0: disable 1: enable 0 7:5 - - reserved 0 4 r/w tx0q_en tx0q enable 0: disable 1: enable 1 3 r/w tx1q_en tx1q enable 0: disable 1: enable 0 2 r/w tx2q_en tx2q enable 0: disable 1: enable 1 1 r/w rx0q_ en rx0q enable 0: disable 1: enable 1 0 - - reserved 0 max_pcnt: max_pcnt register (offset: 0x040c) bits type name description initial value 31:24 r/w max_tx0q_pcnt maximum buffer page count of tx0q. 8h1f 8h3f 8h9f 8h9f free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 189 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 10 w1c write_tx1q manual write tx1q. 0 9 w1c write_tx2q manual write tx2q 0 8 w1c write_rx0q manual write rx0q 0 7 w1c null0 _kick kick out null0 frame. this bit will be cleared after null0 frame is transmitted. 0 6 w1c null1 _kick kick out null1 frame. this bit will be cleared after null1 frame is transmitted. 0 5 w1c buf_reset buffer reset. 0 4 - - reserved 0 3 w1c read_tx0q manual read tx0q. 0 2 w1c read_tx1q manual read tx1q. 0 1 w1c read_tx2q manual read tx2q 0 0 w1c read_rx0q manual read rx0q 0 mcu_int_sta : mcu_int_sta register (offset:0x0414) bits type name description initial value 31:28 - - reserved 0 27 r/w mac_int_11 mac interrupt 11: reserved 0 26 r/w mac_int_10 mac interrupt 10: reserved 0 25 r/w mac_int_9 mac interrupt 9 : reserved 0 24 r/w mac_int_8 mac interrupt 8 : rx qos cf - poll interrupt 0 23 r/w mac_int_7 mac interrupt 7 : txop early termination interrupt 0 22 r/w mac_int_6 mac interrupt 6 : txop early timeout interrupt 0 21 r/w mac_i nt_5 mac interrupt 5 : reserved 0 20 r/w mac_int_4 mac interrupt 4 : gp timer interrupt 0 19 r/w mac_int_3 mac interrupt 3 : auto wakeup interrupt 0 18 r/w mac_int_2 mac interrupt 2 : tx status interrupt 0 17 r/w mac_int_1 mac interrupt 1 : pre - tbtt interru pt 0 16 r/w mac_int_0 mac interrupt 0 : tbtt interrupt 0 15:12 - - reserved 0 11 r/w dtx0_int dma to tx0q frame transfer complete interrupt. 0 10 r/w dtx1_int dma to tx1q frame transfer complete interrupt. 0 9 r/w dtx2_int dma to tx2q frame transfer co mplete interrupt. 0 8 r/w drx0_int rx0q to dma frame transfer complete interrupt. 0 7 r/w hcmd_int host command interrupt. 0 6 r/w n0tx_int null0 frame tx complete interrupt. 0 5 r/w n1tx_int null1 frame tx complete interrupt. 0 4 r/w bcntx_int beacon frame tx complete interrupt. 0 3 r/w mtx0_int tx0q to mac frame transfer complete interrupt. 0 2 r/w mtx1_int tx1q to mac frame transfer complete interrupt. 0 1 r/w mtx2_int tx2q to mac frame transfer complete interrupt. 0 0 r/w mrx0_int mac to rx0q f rame transfer complete interrupt. 0 *this register is only for 8051. mcu_int_ena: mcu_int_ena register (offset: 0x0418) bits type name description initial value 31:28 - - reserved 0 27 r/w mac_int11 _en mac interrupt 11 enable 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 190 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 26 r/w mac_int10 _en mac interrupt 10 enable 0 25 r/w mac_int9 _en mac interrupt 9 enable 0 24 r/w mac_int8 _en mac interrupt 8 enable 0 23 r/w mac_int7 _en mac interrupt 7 enable 0 22 r/w mac_int6 _en mac interrupt 6 enable 0 21 r/w mac_int5 _en mac interrupt 5 enable 0 20 r/w m ac_int4 _en mac interrupt 4 enable 0 19 r/w mac_int3 _en mac interrupt 3 enable 0 18 r/w mac_int2 _en mac interrupt 2 enable 0 17 r/w mac_int1 _en mac interrupt 1 enable 0 16 r/w mac_int0 _en mac interrupt 0 enable 0 15:12 - - reserved 0 11 r/w dtx0_int_e n dma to tx0q frame transfer complete interrupt enable. 0 10 r/w dtx1_int_en dma to tx1q frame transfer complete interrupt enable. 0 9 r/w dtx2_int_en dma to tx2q frame transfer complete interrupt enable. 0 8 r/w drx0_int_en rx0q to dma frame transfer c omplete interrupt enable. 0 7 r/w hcmd_int_en host command interrupt enable. 0 6 r/w n0tx_int_en null0 frame tx complete interrupt enable. 0 5 r/w n1tx_int_en null1 frame tx complete interrupt enable. 0 4 r/w bcntx_int_en beacon frame tx complete inter rupt enable. 0 3 r/w mtx0_int_en tx0q to mac frame transfer complete interrupt enable. 0 2 r/w mtx1_int_en tx1q to mac frame transfer complete interrupt enable. 0 1 r/w mtx2_int_en tx2q to mac frame transfer complete interrupt enable. 0 0 r/w mrx0_int_ en mac to rx0q frame transfer complete interrupt enable. 0 *this register is only for 8051. tx0q_io: tx0q_io register (offset: 0x041c) bits type name description initial value 31:16 - - reserved 0 15:0 r/w tx0q_io tx0q io port. this register is used in manual mode. 0 tx1q_io: tx1q_io register (offset: 0x0420) bits type name description initial value 31:16 - - reserved 0 15:0 r/w tx1q_io tx1q io port. this register is used in manual mode. 0 tx2q_io: tx2q_io register (offset: 0x0424) bits type name des cription initial value 31:16 - - reserved 0 15:0 r/w tx2q_io tx2q io port. this register is used in manual mode. 0 rx0q_io: rx0q_io register (offset: 0x0428) bits type name description initial value 31:16 - - reserved 0 15:0 r/w rx0q_io rx0q io port. this register is used in manual mode. 0 bcn_offset0: bcn_offset0 register (offset: 0x042c) bits type name description initial value 31:24 r/w bcn3_offset beacon #3 address offset in shared memory. unit is 64 byte. 8hec 8he8 8he4 8he0 8hfc free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 191 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 23:16 r/w bcn6_offset beacon #6 address offset in shared memory. unit is 64 byte. 8hf8 15:8 r/w b cn5_offset beacon #5 address offset in shared memory. unit is 64 byte. 8hf4 7:0 r/w bcn4_offset beacon #4 address offset in shared memory. unit is 64 byte. 8hf0 txrxq_sta: txrxq_sta register (offset: 0x0434) bits type name description initial value 31 :24 ro rx0q_sta rxq status 8h22 8h02 8h02 8h02 8h00 8h00 8h00 8h00 8hfe 13h140 13h000 3.20.3.3 register description C rf cfg (base: 1018.0000) rf_csr_cfg: rf_csr_cfg register (offset: 0x0500) bits type name description init value 31:18 r - reserved 0 17 r/w1 rf_csr_kick write C read C C C free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 192 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 25 r/w test_rf_pa_pe_g1 rf_pa_pe_g0 value for rx path 1 in test mode 0 24 r/w test_rf_dc_cal_en1 r f_dc_cal_en value for rx path 1 in test mode 0 23 r - reserved 22:21 r/w test_rf_lna1 rf_lna value for rx path 1 in test mode 0 20:16 r/w test_rf_vga1 rf vga value for rx path 1 in test mode 0 15:13 r - reserved 12 r/w testcsr_rf_pe rf_pe value in t est mode 0 11 r/w testcsr_rf_tr rf_tr value in test mode 0 10 r/w test_rf_ldo123_pe ldo123_pe value in test mode 0 9 r/w test_rf_pa_pe_g0 rf_pa_pe_g0 value for rx path 0 in test mode 0 8 r/w test_rf_dc_cal_en0 rf_dc_cal_en value for rx path 0 in test m ode 0 7 r - reserved 6:5 r/w test_rf_lna0 rf_lna value for rx path 0 in test mode 0 4:0 r/w test_rf_vga0 rf vga value for rx path 0 in test mode 0 rf_test_co ntrol: rf_test_contro l register (offset: 0x0508) bits type name description init value 31:1 r - reserved 0 0 r/w bypass_rf when set, rf control signals come from rf_setting instead of mac/bbp in normal operation mode 0 3.20.3.4 register description - mac (base: 1018.0000) asic_ver_id: asic_ver_id register (offset: 0x1000) bits type name description initi al value 31:16 r ver_id asic version id 16h2860 16h0101 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 193 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 1: enable 0: disable 1 r/w bbp_hrst bbp hard - reset 1: bbp in reset state 0: bbp in normal state note: whole bbp including bbp registers will be reset. 1 0 r/w mac_srst mac soft - reset 1: mac in reset state 0: mac in normal state note: mac registers and tables will not be re set. 1 note: mac hard - reset is outside the scope of mac registers. mac_addr_dw0: mac_addr_dw0 register (offset: 0x1008) bits type name description initial value 31:24 r/w mac_addr_3 mac address byte3 0 23:16 r/w mac_addr_2 mac address byte2 0 15:8 r/w mac_addr_1 mac address byte1 0 7:0 r/w mac_addr_0 mac address byte0 0 mac_addr_dw1: mac_addr_dw1 register (offset: 0x100c) bits type name description initial value 31:16 - - reserved 0 15:8 r/w mac_addr_5 mac address byte5 0 7:0 r/w mac_addr_4 mac add ress byte4 0 note: byte0 is the first byte on network. its lsb bit is the first bit on network. for a mac address captured on the network with order 00:01:02:03:04:05, byte0=00, byte1 =01 etc. mac_bssid_dw0: mac_bssid_dw0 register (offset: 0x1010) bits typ e name description initial value 31:24 r/w bssid_3 bssid byte3 0 23:16 r/w bssid_2 bssid byte2 0 15:8 r/w bssid_1 bssid byte1 0 7:0 r/w bssid_0 bssid byte0 0 mac_bssid_dw1: mac_bssid_dw1 register (offset: 0x1014) bits type name description initial val ue 31:21 - - reserved 0 20:18 r/w multi_bcn_num multiple bssid beacon number 0: one back - off beacon 1 - 7: sifs - burst beacon count 0 17:16 r/w multi_bssid_mode multiple bssid mode in multiple - bssid ap mode, bssid shall be the same as mac_addr, that is, this device owns multiple mac_addr in this mode. the multiple mac_addr/bssid are distinguished by [bit2: bit0] of byte5. 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 194 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0: 1 - bssid mode (bss index = 0) 1: 2 - bssid mode (byte5.bit0 as bss index) 2: 4 - bssid mode (byte5.bit1:0 as bss index) 3: 8 - bssid mode (byte5.bit2:0 as bss index) 15:8 r/w bssid_5 bssid byte5 0 7:0 r/w bssid_4 bssid byte4 0 max_len_cfg: max_len_cfg register (offset: 0x1018) bits type name description initial value 31:20 - - reserved 0 19:16 r/w min_mpdu_len minimum mpdu length (un it: bytes) mac will drop the mpdu if the length is less than this limitation. applied only in mac rx. 10 15:14 - - reserved 0 13:12 r/w max_psdu_len maximum psdu length (power factor) 0: 2^13 = 8k bytes 1: 2^14 = 16k bytes 2: 2^15 = 32k bytes 3: 2^16 = 64k bytes mac will not generate a - mpdu with length gr eater than this limitation. applied only in mac tx. 0 11:0 r/w max_mpdu_len maximum mpdu length (unit: bytes) mac will drop the mpdu if the length is greater than this limitation. applied only in mac rx. 4095 bbp_csr_cfg: bbp_csr_cfg register (offset: 0x101c) bits type name description initial value 31:20 - - reserved 0 19 r/w bbp_rw _mode bbp register r/w mode 1: parallel mode 0: serial mode 1 18 r/w bbp_par_dur bbp register parallel r/w pulse wid th 0: pulse width = 62.5ns 1: pulse width = 112.5ns note: please set bbp_par_dur=1 in 802.11j mode. 0 17 r/w bbp_csr_kick write - kick bbp register read/write 0: do nothing 1: kick read/write process read - polling bbp register read/write progress 0: id le, 1: busy 0 16 r/w bbp_csr_rw 0: write 1: read 0 15:8 r/w bbp_addr bbp register id 0 for r0, 1 for r1, and so on. 0 7:0 r/w bbp_data write - data written to bbp read - data read from bbp 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 195 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years rf_csr_cfg0: rf_csr_cfg0 register (offset: 0x1020) bits type name description initial value 31 r/w rf_reg_ctrl write: 1 - rf_reg0/1/2 to rf chip read: 0 C note: software should make sure the first bit (msb in the specified bit number) written to rf is 0 for rf chip mode selection) led_cfg: led_cfg register (offset: 0x102c) bits typ e name description initial value 31 - - reserved 0 30 r/w led_pol led polarity 0: active low 1: active high 0 29:28 r/w y_led_mode yellow led mode 0: off 1: blinking upon tx 2: periodic slow blinking 3: always on 0 27:26 r/w g_led_mode green led mode 0 : off 1: blinking upon tx 2: periodic slow blinking 3: always on 2 25:24 r/w r_led_mode red led mode 0: off 1: blinking upon tx 1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 196 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2: periodic slow blinking 3: always on 23:22 - - reserved 0 21:16 r/w slow_blk_time slow blinking period (unit: 1sec) 3 15 :8 r/w led_off_time tx blinking off period (unit: 1ms) 30 7:0 r/w led_on_time tx blinking on period (unit: 1ms) 70 ampdu_max_len_20m1s: ampdu_max_len_20m1s register (offset: 0x1030) bits type name description initial value 31:28 r/w ampdu_max_bw20_mcs7 maximum ampdu for bw20 mcs7* 7 27:24 r/w ampdu_max_bw20_mcs6 maximum ampdu for bw20 mcs6* 7 23:20 r/w ampdu_max_bw20_mcs5 maximum ampdu for bw20 mcs5* 7 19:16 r/w ampdu_max_bw20_mcs4 maximum ampdu for bw20 mcs4* 7 15:12 r/w ampdu_max_bw20_mcs3 maximum ampdu for bw20 mcs3* 7 11:08 r/w ampdu_max_bw20_mcs2 maximum ampdu for bw20 mcs2* 7 07:04 r/w ampdu_max_bw20_mcs1 maximum ampdu for bw20 mcs1* 7 03:00 r/w ampdu_max_bw20_mcs0 maximum ampdu for bw20 mcs0* 7 note1*: 0 - 2: 2k bytes, 3: 4k bytes, 4: 8k, 5: 16k, 6: 32k, 7: 64k note2: the value applied together with 0x1018 max_psdu_len. ampdu_max_len_20m2s: ampdu_max_len_20m2s register (offset: 0x1034) bits type name description initial value 31:28 r/w ampdu_max_bw20_mcs15 maximum ampdu for bw20 mcs15* 7 27: 24 r/w ampdu_max_bw20_mcs14 maximum ampdu for bw20 mcs14* 7 23:20 r/w ampdu_max_bw20_mcs13 maximum ampdu for bw20 mcs13* 7 19:16 r/w ampdu_max_bw20_mcs12 maximum ampdu for bw20 mcs12* 7 15:12 r/w ampdu_max_bw20_mcs11 maximum ampdu for bw20 mcs11* 7 11: 08 r/w ampdu_max_bw20_mcs10 maximum ampdu for bw20 mcs10* 7 07:04 r/w ampdu_max_bw20_mcs9 maximum ampdu for bw20 mcs9* 7 03:00 r/w ampdu_max_bw20_mcs8 maximum ampdu for bw20 mcs8* 7 note1*: 0 - 2: 2k bytes, 3: 4k bytes, 4: 8k, 5: 16k, 6: 32k, 7: 64k note2 : the value applied together with 0x1018 max_psdu_len. ampdu_max_len_40m1s: ampdu_max_len_40m1s register (offset: 0x1038) bits type name description initial value 31:28 r/w ampdu_max_bw40_mcs7 maximum ampdu for bw40 mcs7* 7 27:24 r/w ampdu_max_bw40_mcs6 maximum ampdu for bw40 mcs6* 7 23:20 r/w ampdu_max_bw40_mcs5 maximum ampdu for bw40 mcs5* 7 19:16 r/w ampdu_max_bw40_mcs4 maximum ampdu for bw40 mcs4* 7 15:12 r/w ampdu_max_bw40_mcs3 maximum ampdu for bw40 mcs3* 7 11:08 r/w ampdu_max_bw40_mcs2 maximum ampdu for bw40 mcs2* 7 07:04 r/w ampdu_max_bw40_mcs1 maximum ampdu for bw40 mcs1* 7 03:00 r/w ampdu_max_bw40_mcs0 maximum ampdu for bw40 mcs0* 7 note1*: 0 - 2: 2k bytes, 3: 4k bytes, 4: 8k, 5: 16k, 6: 32k, 7: 64k note2: the value applied together with 0x1 018 max_psdu_len. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 197 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ampdu_max_len_40m2s: ampdu_max_len_40m2s register (offset: 0x103c) bits type name description initial value 31:28 r/w ampdu_max_bw40_mcs15 maximum ampdu for bw40 mcs15* 7 27:24 r/w ampdu_max_bw40_mcs14 maximum ampdu for bw40 mcs14* 7 23:20 r/w ampdu_max_bw40_mcs13 maximum ampdu for bw40 mcs13* 7 19:16 r/w ampdu_max_bw40_mcs12 maximum ampdu for bw40 mcs12* 7 15:12 r/w ampdu_max_bw40_mcs11 maximum ampdu for bw40 mcs11* 7 11:08 r/w ampdu_max_bw40_mcs10 maximum ampdu for bw40 mcs10* 7 07:04 r/w ampdu_max_bw40_mcs9 maximum ampdu for bw40 mcs9* 7 03:00 r/w ampdu_max_bw40_mcs8 maximum ampdu for bw40 mcs8* 7 note1*: 0 - 2: 2k bytes, 3: 4k bytes, 4: 8k, 5: 16k, 6: 32k, 7: 64k note2: the value applied together with 0x1018 max_psdu_len. ampdu_ ba_winsize: ampdu_ba_winsize register ( (offset: 0x1040) bits type name description initial value 31:07 r - reserved 0 -- :06 r/w force_ba_winsize_en enable forced ba window size over ba window size value in txwi 0: disable, 1: enable 0 05:00 r/w force_ ba_winsize forced ba window size 0 xifs_time_cfg: xifs_time_cfg register (offset:0x1100) bits type name description initial value 31:30 - - reserved 29 r/w bb_rxend_en bb_rx_end signal enable refer bb_rx_end signal from bbp rx logic to start sifs defe r. 0: disable 1: enable 1 28:20 r/w eifs_time eifs time (unit: 1us) eifs is the defer time after reception of a crc error packet. after deferring eifs, the nor mal back - off process may proceed. 314 19:16 r/w ofdm_xifs_time delayed ofdm sifs time compen sator (unit: 1us) when bb_rx_end from bbp is a delayed version the sifs deferred will be (ofdm_sifs_time - ofdm_xifs_time) 4 15:8 r/w ofdm_sifs_time ofdm sifs time (unit: 1us) applied after ofdm tx/rx. 16 7:0 r/w cck_sifs_time cck sifs time (unit: 1us) applied after cck tx/rx. 10 note1: eifs = sifs + ack @ 1mbps + difs = 10us (sifs) + 192us (long preamble) + 14*8us (ack) + 50us (difs) = 364. however, mac should start back - off procedure after (eifs - difs). note2: eifs is not applied if mac is a txop i nitiator that owns the channel. note3: eifs is not started if ampdu is only partial corrupted. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 198 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years caution: it is recommended that both (cck_sifs_time) and (ofdm_sifs_time) are no less than tx/rx transition time. if the sifs value is not long enough, a sifs burst transmission may be replaced with a pifs burst one. bkoff_slot_cfg: bkoff_slot_cfg register (offset: 0x1104) bits type name description initial value 31:12 - - reserved 0 11:8 r/w cc_delay_time channel clear delay (unit: 1 - us) this value specified the tx guard time after channel is clear. 2 7:0 r/w slot_time slot time (unit: 1 - us) this value specified the slot boundary after deferring sifs time. note: default 20us is for 11b/g. 11a and 11g - short - slot - mode is 9us. 20 nav_time_cfg: nav_time_cfg r egister (offset: 0x1108) bits type name description initial value 31 wc nav_upd nav timer manual update command 0: do nothing 1: update nav timer with nav_upd_val 0 30:16 r/w nav_upd_val nav timer manual update value (unit: 1us) 0 15 r/w nav_clr_en nav timer auto - clear enable when enabled, mac will auto clear nav timer after the reception of cf - end frame from previous nav holder sta. 0: disable 1: enable 1 14:0 r nav_timer nav timer (unit: 1us) the timer is set by other sta and will auto countdown t o zero. the sta who set the nav timer is called the nav holder. when nav timer is nonzero, mac will not send any packet. 0 ch_time_cfg: ch_time_cfg register (offset: 0x110c) bits type name description initial value 31:5 - - reserved 0 4 r/w eifs_as_ch_b usy count eifs as channel busy 0: disable 1: enable 1 3 r/w nav_as_ch_busy count nav as channel busy 0: disable 1: enable 1 2 r/w rx_as_ch_busy count rx busy as channel busy 0: disable 1: enable 1 1 r/w tx_as_ch_busy count tx busy as channel busy 0: dis able 1: enable 1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 199 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0 r/w ch_sta_timer_en channel statistic timer enable 0: disable 1: enable 0 pbf_life_timer: pbf_life_timer register (offset: 0x1110) bits type name description initial value 31:0 r pbf_life_timer tx/rx mpdu timestamp timer (free run) un it: 1us 0 bcn_time_cfg: bcn_time_cfg register (offset: 0x1114) bits type name description initial value 31:24 r/w tsf_ins_comp tsf insertion compensation value (unit: 1us) when inserting tsf, add this value with local tsf timer as the tx timestamp. 0 2 3:21 - - reserved 0 20 r/w bcn_tx_en beacon frame tx enable when enabled, mac sends beacon frame at tbtt interrupt. 0: disable 1: enable 0 19 r/w tbtt_timer_en tbtt timer enable when enabled, tbtt interrupt will be issued periodically with period spec ified in (bcn_intval). 0: disable 1: enable 0 18:17 r/w tsf_sync_mode local 64 - bit tsf timer synchronization mode 00: disable 01: (sta infra - structure mode) upon the reception of beacon frame from associated bss, local tsf is always updated with remote t sf. 10: (sta ad - hoc mode) upon the reception of beacon frame from associated bss, local tsf is updated with remote tsf only if the remote tsf is greater than local tsf. 11: (ap mode) sync with nobody 0 16 r/w tsf_timer_en local 64 - bit tsf timer enable wh en enabled, tsf timer will re - start from zero. 0: disable 1: enable 0 15:0 r/w bcn_intval beacon interval (unit: 64us) this value specified the interval between maximum beacon interval is about 4sec. 1600 tbtt_sync_cfg: tbtt_sync_cfg register (offset : 0x1118) bits type name description initial value 31:24 - - reserved 0 23:20 r/w bcn_cwmin beacon transmission cwmin after tbtt interrupt (unit: 4 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 200 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years slot) 19:16 r/w bcn_aifsn beacon transmission aifsn after tbtt interrupt (unit: slot) 2 15:8 r/w bcn_exp _win beacon expecting window duration (unit: 64us) the window starts from tbtt interrupt. the phase of tbtt interrupt train will not be adjusted by the beacon arrived within the window. 32 7:0 r/w tbtt_adjust ibss mode tbtt phase adaptive adjustment st ep (unit: 1us), default value is 16us. in ibss mode (ad hoc), if consecutive tx beacon failures (or consecutive success) happened, tbtt timer will adjust it phase to meet the external ad hoc tbtt time. 16 tsf_timer_dw0: tsf_timer_dw0 register (offset: 0x 111c) bits type name description initial value 31:0 r tsf_timer_dw0 local tsf timer lsb 32 bits (unit: 1us) 0 tsf_timer_dw1: tsf_timer_dw1 register (offset: 0x1120) bits type name description initial value 31:0 r tsf_timer_dw1 local tsf timer msb 32 bit s (unit: 1us) 0 tbtt_timer: tbtt_timer _dw0 register (offset: 0x1124) bits type name description initial value 31:17 - - reserved 0 16:0 r tbtt_timer tbtt timer (unit: 32us) the time remains till next tbtt. when tbtt_timer_en is enabled, the timer wil l down count from bcn_intval to zero. when tbtt_timer_en is disabled, the timer will stay in zero. 0 int_timer_cfg: int_timer_cfg register (offset: 0x1128) bits type name description initial value 31:16 r/w gp_timer period of general purpose interrupt t imer (unit: 64us) 0 15:0 r/w pre_tbtt_timer pre - tbtt interrupt time (unit: 64us) the value specified the interrupt timing before tbtt interrupt. 0 int_timer_en: int_timer_en register (offset: 0x112c) bits type name description initial value 31:2 - - r eserved 0 1 r/w gp_timer_en periodic general purpose interrupt timer enable 0: disable 1: enable 0 0 r/w pre_tbtt_int_en pre - tbtt interrupt enable 0: disable 1: enable 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 201 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ch_idle_sta: ch_idle_sta register (offset: 0x1130) bits type name description ini tial value 31:0 rc ch_idle_time channel idle time unit: 1us 0 in application, the channel busy time can be derived by the equation: ch_busy_time = host polling period C ch_idle_time. reserved: reserved register (offset: 0x1134) bits type name description initial value 31:0 rc reserved reserved 0 mac_status_reg: mac_status_reg register (offset: 0x1200) bits type name description initial value 31:2 - - reserved 0 1 r rx_status rx status 0: idle 1: busy 0 0 r tx_status tx status 0: idle 1: busy 0 pwr_p in_cfg: pwr_pin_cfg register (offset: 0x1204) bits type name description initial value 31:4 - - reserved 0 3 r/w io_adda_pd ad/da power down 0 2 r/w io_pll_pd pll power down 0 1 r/w io_ra_pe ra_pe 1 0 r/w io_rf_pe rf_pe 1 auto_w akeup_cfg: auto _wakeup _cfg register (offset:0x1208) bits type name description initial value 31:16 - - reserved 0 15 r/w auto_w akeup_en auto wakeup interrupt enable auto wakeup interrupt will be issued after #(sleep_tbtt_num) tbtts at wakeup_lead_time 0: disable 1: enable note: please make sure tbtt_timer_en is enabled. 0 14:8 r/w sleep_tbtt_num number of sleeping tbtt 0 7:0 r/w wakeup_lead_tim e auto wakeup lead time (unit: 1tu=1024us) 20 3.20.3.5 mac tx configuration registers (base: 1018.0000) edc a_ac0_cfg (be): edca_ac0_cfg (be) register (offset: 0x1300) bits type name description initial value 31:20 - - reserved 0 19:16 r/w ac0_cw max ac0 cwmax (unit: power of 2) 7 15:12 r/w ac0_cw min ac0 cwmin (unit: power of 2) 3 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 202 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 11:8 r/w ac0_aifsn ac0 aifsn (unit: # of slot time) 2 7:0 r/w ac0_txop ac0 txop limit (unit: 32us) 0 edca_ac1_cfg (bk): edca_ac1_cfg (bk) register (offset: 0x1304) bits type name description initial value 31:20 - - reserved 0 19:16 r/w ac1_cw max ac1 cwmax (unit: power of 2) 7 15 :12 r/w ac1_cw min ac1 cwmin (unit: power of 2) 3 11:8 r/w ac1_aifsn ac1 aifsn (unit: # of slot time) 2 7:0 r/w ac1_txop ac1 txop limit (unit: 32us) 0 edca_ac2_cfg (vi): edca_ac2_cfg (vi) register (offset: 0x1308) bits type name description initial value 31:20 - - reserved 0 19:16 r/w ac2_cw max ac2 cwmax (unit: power of 2) 7 15:12 r/w ac2_cw min ac2 cwmin (unit: power of 2) 3 11:8 r/w ac2_aifsn ac2 aifsn (unit: # of slot time) 2 7:0 r/w ac2_txop ac2 txop limit (unit: 32us) 0 edca_ac3_cfg (vo): edca_a c3 _cfg (vo) register (offset: 0x130c) bits type name description initial value 31:20 - - reserved 0 19:16 r/w ac3_cw max ac3 cwmax (unit: power of 2) 7 15:12 r/w ac3_cw min ac3 cwmin (unit: power of 2) 3 11:8 r/w ac3_aifsn ac3 aifsn (unit: # of slot time ) 2 7:0 r/w ac3_txop ac3 txop limit (unit: 32us) 0 edca_tid_ac_map: edca_tid_ac_map register (offset: 0x1310) bits type name description initial value 31:16 - - reserved 0 15:14 r/w tid7_ac_map ac value as tid=7 3 13:12 r/w tid6_ac_map ac value as tid =6 3 11:10 r/w tid5_ac_map ac value as tid=5 2 9:8 r/w tid4_ac_map ac value as tid=4 2 7:6 r/w tid3_ac_map ac value as tid=3 0 5:4 r/w tid2_ac_map ac value as tid=2 1 3:2 r/w tid1_ac_map ac value as tid=1 1 1:0 r/w tid0_ac_map ac value as tid=0 0 no te: default according 802.11e table 20.23 user priority to access category mappings. tx_pwr_cfg_0: tx_pwr_cfg_0 register (offset: 0x1314, default: 0x6666_6666) bits type name description initial value 31:24 r/w tx_pwr_ofdm_12 tx power for ofdm 12m/18m 0x6 6 23:16 r/w tx_pwr_ofdm_6 tx power for ofdm 6m/9m 0x66 15:8 r/w tx_pwr_cck_5 tx power for cck5.5m/11m 0x66 7:0 r/w tx_pwr_cck_1 tx power for cck1m/2m 0x66 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 203 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_pwr_cfg_1: tx_pwr_cfg_1 register (offset: 0x1318) bits type name description initial value 31:24 r/w tx_pwr_mcs_2 tx power for ht mcs=2,3 0x66 23:16 r/w tx_pwr_mcs_0 tx power for ht mcs=0,1 0x66 15:8 r/w tx_pwr_ofdm_48 tx power for ofdm 48m/54m 0x66 7:0 r/w tx_pwr_ofdm_24 tx power for ofdm 24m/36m 0x66 tx_pwr_cfg_2: tx_pwr_cfg_2 register (of fset: 0x131c) bits type name description initial value 31:24 r/w tx_pwr_mcs_10 tx power for ht mcs=10,11 0x66 23:16 r/w tx_pwr_mcs_8 tx power for ht mcs=8,9 0x66 15:8 r/w tx_pwr_mcs_6 tx power for ht mcs=6,7 0x66 7:0 r/w tx_pwr_mcs_4 tx power for ht mc s=4,5 0x66 tx_pwr_cfg_3: tx_pwr_cfg_3 register (offset: 0x1320) bits type name description initial value 31:24 r/w - reserved 0x66 23:16 r/w - reserved 0x66 15:8 r/w tx_pwr_mcs_14 tx power for ht mcs=14,15 0x66 7:0 r/w tx_pwr_mcs_12 tx power for ht mc s=12,13 0x66 tx_pwr_cfg_4: tx_pwr_cfg_4 register (offset: 0x1324) bits type name description initial value 31:16 - - reserved 0 15:8 r/w - reserved 0x66 7:0 r/w - reserved 0x66 tx_pin_cfg: tx_pin_cfg register (offset: 0x1328) bits type name descriptio n initial value 31:20 - - reserved 0 19 r/w trsw_po l trsw_en polarity 0 18 r/w trsw_en trsw_en enable 1 17 r/w rftr_pol rf_tr polarity 0 16 r/w rftr_en rf_tr enable 1 15 r/w lna_pe_g1_po l lna_pe_g1 polarity 0 14 r/w lna_pe_a1 _pol lna_pe_a1 polarity 0 13 r/w lna_pe_g0_po l lna_pe_g0 polarity 0 12 r/w lna_pe_a0 _pol lna_pe_a0 polarity 0 11 r/w lna_pe_g1_en lna_pe_g1 enable 1 10 r/w lna_pe_a1 _en lna_pe_a1 enable 1 9 r/w lna_pe_g0_en lna_pe_g0 enable 1 8 r/w lna_pe_a0 _en lna_pe_a0 enable 1 7 r/w pa_ pe_g1_pol pa_pe_g1 polarity 0 6 r/w pa_pe_a1_po l pa_pe_a1 polarity 0 5 r/w pa_pe_g0_pol pa_pe_g0 polarity 0 4 r/w pa_pe_a0_po l pa_pe_a0 polarity 0 3 r/w pa_pe_g1_en pa_pe_g1 enable 1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 204 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 2 r/w pa_pe_a1_en pa_pe_a1 enable 1 1 r/w pa_pe_g0_en pa_pe_g0 enab le 1 0 r/w pa_pe_a0_en pa_pe_a0 enable 1 tx_band_cfg: tx_band_cfg register (offset: 0x132c) bits type name description initial value 31:3 - - reserved 0 2 r/w 5g_band_sel_n 5g band selection pin (complement of 5g_band_sel_p) 1 1 r/w 5g_band_sel_p 5g b and selection pin 0 0 r/w tx_band_sel 0: use lower 40mhz band in 20mhz tx 1: use upper 40mhz band in 20mhz tx 0 note1: tx_band_sel is effective only when tx/rx bandwidth control register r4 of bbp is set to 40mhz. tx_sw _cfg0 : tx_sw_cfg0 register (offset: 0x1330) bits type name description initial value 31:24 r/w dly_rftr_en delay of rf_tr assertion 0x0 23:16 r/w dly_trsw_en delay of tr_sw assertion 0x4 15:8 r/w dly_pape_en delay of pa_pe assertion 0x8 7:0 r/w dly_txpe_en delay of tx_pe assertion 0xc note1: the timing unit is 0.25us. note2: sifs_time should compensate with dly_txpe_en. tx_sw _cfg1 : tx_sw_cfg1 register (offset: 0x1334) bits type name description initial value 31:24 - - reserved 0 23:16 r/w dly_rftr_dis delay of rf_tr de - assertion 0xc 15:8 r/w dly_trsw_dis delay of tr_sw de - assertion 0x8 7:0 r/w dly_pape_dis delay of pa_pe de - assertion 0x8 note1: the timing unit is 0.25us. note2: the delay is started from tx_end event of bbp. note3: tx_pe is de - asserted automatically as last data byte passed to bbp. tx_sw _cfg2 : tx_sw_cfg2 register (offset: 0x1338) bits type name description initial value 31:24 r/w dly_lna_en delay of lna* assertion 0x0 23:16 r/w dly_lna_dis delay of lna* de - assertion 0xc 15:8 r/w dly_dac_en delay of dac_pe assertion 0x4 7:0 r/w dly_dac_dis delay of dac_pe de - assertion 0x8 note1: the timing unit is 0.25us. note 2: lna* includes lna_a0, lna_a1, lna_g0, lna_g1. txop_thres_cfg: txop_thres_cfg register (offset: 0x133c) bits type name description initial value 31:24 r/w txop_rem_thres remaining txop threshold, unit: 32us as the remaining txop is less than the threshold, the txop is passed silently. 0 23:16 r/w cf_end_thres cf - end threshold, unit: 32us as the remaining txop is greater than the threshold, the 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 205 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years cf - end wil l be send to release the remaining txop reserved by long nav. set 0xff to disable cf_end transmission. 15:8 r/w rdg_in_thres rx rdg threshold, unit: 32us as the remaining txop (specified in the duration field of the rx frame with rdg=1) is greater tha n or equal to the threshold, the granted reverse direction txop may be used. 0 7:0 r/w rdg_out_thres tx rdg threshold, unit: 32us as the remaining txop is greater than or equal to the threshold, rdg in the tx frame may be set to one. 0 txop_ctrl_cfg: tx op_ctrl_cfg register (offset: 0x1340) bits type name description initial value 31:20 - - reserved 0 19:16 r/w ext_cw_min cwmin for extension channel backoff when ext_cca_en is enabled, 40mhz transmission will be suppressed to 20mhz if the extension cca is busy or extension channel backoff is not finished. default: cwmin=0, disable. 0 15:8 r/w ext_cca_dly extension cca signal delay time (unit: usec) create delayed version of extension cca signal reference time for extension channel ifs. default: (ofdm sifs) + (long slot time) = 16 + 20 = 36 (usec) 36 7 r/w ext_cca_en extension cca reference enable when transmit in 40mhz mode, defer until extension cca is also clear. 0: disable 1: enable 0 6 r/w lsig_txop_en l - sig txop protection enable extension o f mix mode l - sig protection range to following ack/cts. 0 5:0 r/w txop_trun_en txop truncation enable bit5: reserved bit4: truncation for mimo power save rts/cts bit3: truncation for user txop mode bit2: truncation for tx rate group change bit1: truncati on for ac change bit0: txop timeout truncation 0: disable 1: enable 0x3f free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 206 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_rts_cfg: tx_rts_cfg register (offset: 0x1344) bits type name description initial value 31:24 - - reserved 0 24 r/w rts_fbk_en rts rate fallback enable 0 23:8 r/w rts_thres r ts thr eshold (unit: byte) mpdu or ampdu with length gr eater than rts threshold will be protected with rts/cts exchange at the beginning of the txop. 65535 7:0 r/w rts_rty_limit auto rts retry limit 7 tx_timeout_cfg: tx_timeo ut_cfg register (offset: 0x13 48) bits type name description initial value 31:24 - - reserved 0 23:16 r/w txop_timeout txop timeout value for txop truncation unit: 1usec note: it is recommended that (slot_time) > (txop_timeout) > (rx_ack_timeo ut) default: for 20us long slot time. 1 5 15:8 r/w rx_ack_timeout rx ack/cts timeout value for tx procedure unit: 1usec note: it is recommended that (slot_time) > (txop_timeout) > (rx_ack_timeo ut) default: for 20us long slot time. 10 7:4 r/w mpdu_life_time tx mpdu expiration time expiration time = 2^(9+mpdu_life_time) us default value is 2^(9+9) ~= 256ms 9 3:0 - - reserved 0 tx_rty_cfg: tx_rty_cfg register (offset: 0x134c) bits type name description initial value 31 - - reserved 0 30 r/w tx_autofb_en tx retry phy rate auto fallback enab le 0: disable 1: enable 0 29 r/w agg_rty_mo de aggr egate mpdu r etry mode 0: expired by retry limit 1: expired by mpdu life timer 1 28 r/w nag_rty_mode non - aggregate mpdu retry mode 0: expired by retry limit 1: expired by mpdu life timer 0 27:16 r/w lo ng_rty_thres long retry threshold mpdu with length over this threshold is applied with long retry limit. 3000 15:8 r/w long_rty_limit long retry limit 4 7:0 r/w short_rty_limit short retry limit 7 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 207 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_link_cfg: tx_link_cfg register (offset: 0x1350) bits type name description initial value 31:24 r remote_mfs remote mcs feedback sequence number * 23:16 r remote_mfb remote mcs feedback 0x7f 15:13 - - reserved 0 12 r/w tx_cfack_en piggyback cf - ack enable 0: disable 1: enable 0 11 r/w tx_rdg_en rdg tx e nable 0: disable 1: enable 0 10 r/w tx_mrq_en mcs request tx enable 0: disable 1: enable 0 9 r/w remote_umfs_en remote un - solicit mfb enable 0: do not apply remote un - solicit mfb (mfs=7) 1: apply un - solicit mfb 0 8 r/w tx_mfb_en tx apply remote mfb 0: disable 1: enable 0 7:0 r/w remote_mfb_lite time remote mfb life time unit: 32us 32 ht_fbk_cfg0: ht_fbk_cfg0 register (offset: 0x1354) bits type name description initial value 31:28 r/w ht_mcs7 _fbk auto fall back mcs as ht mcs =7 6 27:24 r/w ht_mcs6 _fbk auto fall back mcs as ht mcs =6 5 23:20 r/w ht_mcs5 _fbk auto fall back mcs as ht mcs =5 4 19:16 r/w ht_mcs4 _fbk auto fall back mcs as ht mcs =4 3 15:12 r/w ht_mcs3 _fbk auto fall back mcs as ht mcs =3 2 11:8 r/w ht_mcs2 _fbk auto fall back mcs as ht mcs =2 1 7:4 r/w ht_mcs1 _fbk auto fall back mcs as ht mcs =1 0 3:0 r/w ht_mcs0 _fbk auto fall back mcs as ht mcs =0 0 ht_fbk_cfg1: ht_fbk_cfg1 register (offset: 0x1358) bits type name description initial value 31:28 r/w ht_mcs15_fbk auto fall back mcs as ht mcs =15 14 27:24 r/w ht_mcs14_fbk auto fall back mcs as ht mcs =14 13 23:20 r/w ht_mcs13_fbk auto fall back mcs as ht mcs =13 12 19:16 r/w ht_mcs12_fbk auto fall back mcs as ht mcs =12 11 15:12 r/w ht_mcs11_fbk auto fall back mcs as ht mcs =11 10 11:8 r/w ht_mcs10_fbk auto fall back mcs as ht mcs =10 9 7:4 r/w ht_mcs9 _fbk auto fall back mcs as ht mcs =9 8 3:0 r/w ht_mcs8 _fbk auto fall back mcs as ht mcs =8 8 note1. the mcs is a fallback stopping state, as the fallback mcs is the same as curren t mcs. note2. ht tx phy rates will not fallback to legacy phy rates. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 208 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years lg_fbk_cfg0 : lg_fbk_cfg0 register (offset: 0x135c) bits type name description initial value 31:28 r/w ofdm7_fbk auto fall back mcs as previous tx rate is ofdm 54mbps. 14 27:24 r/w ofdm6 _fbk auto fall back mcs as previous tx rate is ofdm 48mbps. 13 23:20 r/w ofdm5_fbk auto fall back mcs as previous tx rate is ofdm 36mbps. 12 19:16 r/w ofdm4_fbk auto fall back mcs as previous tx rate is ofdm 24mbps. 11 15:12 r/w ofdm3_fbk auto fall back mcs as previous tx rate is ofdm 18mbps. 10 11:8 r/w ofdm2_fbk auto fall back mcs as previous tx rate is ofdm 12mbps. 9 7:4 r/w ofdm1_fbk auto fall back mcs as previous tx rate is ofdm 9mbps. 8 3:0 r/w ofdm0_fbk auto fall back mcs as previous tx rate is ofdm 6mbps. 8 lg_fbk_cfg1 : lg_fbk_cfg1 register (offset: 0x1360) bits type name description initial value 31:16 - - reserved 0 15:12 r/w cck3_fbk auto fall back mcs as previous tx rate is cck 11mbps. 2 11:8 r/w cck2_fbk auto fall back mcs as previous tx rate is cck 5.5mbps. 1 7:4 r/w cck1_fbk auto fall back mcs as previous tx rate is cck 2mbps. 0 3:0 r/w cck0_fbk auto fall back mcs as previous tx rate is cck 1mbps. 0 note1. bit3 of each legacy fallback rate is selection of ofdm/cck. 0=cck, 1=ofdm. c ck_prot_cfg: cck_prot_cfg register (offset: 0x1364) bits type name description initial value 31:27 - - reserved 0 26 r/w cck_rtsth_en rts thr eshold enable on cck tx 0: disable 1: enable 0 25:20 r/w cck_txop_allow cck txop allowance (0: disallow, 1: all ow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx bit20: allow cck tx 1 19:18 r/w cck_prot_nav txop protection type for cck tx 0: none 1: short nav protection 2: long nav protection 3: reserve d (none) 0 17:16 r/w cck_prot_ctrl protection control frame type for cck tx 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 0 15:0 r/w cck_prot_rate protection control frame rate for cck tx (including rts/cts - to - self/cf - end) default: cck 11m 0x0003 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 209 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ofdm_pro t_cfg: ofdm_prot_cfg register (offset: 0x1368) bits type name description initial value 31:27 - - reserved 0 26 r/w ofdm_rtsth_en rts thr eshold enable on ofdm tx 0: disable 1: enable 0 25:20 r/w ofdm_pro t_txop ofdm txop allowance (0: disallow , 1: allow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx bit20: allow cck tx 2 19:18 r/w ofdm_pro t_nav txop protection type for ofdm tx 0: none 1: short nav protection 2: long nav protection 3: reserved (none) 0 17:16 r/w ofdm_pro t_ctrl protection control frame type for ofdm tx 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 0 15:0 r/w ofdm_pro t_rate protection control frame rate for ofdm tx (including rts/cts - to - self/cf - end) default: c ck 11m 0x0003 mm20_prot_cfg: mm20_pro t_cfg register (offset: 0x136c) bits type name description initial value 31:27 - - reserved 0 26 r/w mm20_rtsth_en rts thr eshold enable on mm20 tx 0: disable 1: enable 0 25:20 r/w mm20_prot_txop mm20 txop allowance (0: disallow, 1: allow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx bit20: allow cck tx 4 19:18 r/w mm20_prot_nav txop protection type for mm20 tx 0: none 1: short nav protection 2: long na v protection 3: reserved (none) 0 17:16 r/w mm20_prot_ctrl protection control frame type for mm20 tx 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 210 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 15:0 r/w mm20_prot_rate protection control frame rate for mm20 tx (including rts/cts - to - self/cf - en d) default: ofdm 24m 0x4004 mm40_prot_cfg: mm40_pro t_cfg register (offset: 0x1370) bits type name description initial value 31:27 - - reserved 0 26 r/w mm40_rtsth_en rts thr eshold enable on mm40 tx 0: disable 1: enable 0 25:20 r/w mm40_prot_txop mm40 t xop allowance (0: disallow, 1: allow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx bit20: allow cck tx 8 19:18 r/w mm40_prot_nav txop protection type for mm40 tx 0: none 1: short nav protect ion 2: long nav protection 3: reserved (none) 0 17:16 r/w mm40_prot_ctrl protection control frame type for mm40 tx 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 0 15:0 r/w mm40_prot_rate protection control frame rate for mm40 tx (including rts/cts - to - self/cf - end) default: duplicate ofdm 24m 0x4084 gf20_prot_cfg: gf20_prot_cfg register (offset: 0x1374) bits type name description initial value 31:27 - - reserved 0 26 r/w gf20_rtsth_en rts thr eshold enable on gf20 tx 0: disable 1: enable 0 25:20 r /w gf20_prot_txop gf20 txop allowance (0: disallow, 1: allow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx 16 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 211 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years bit20: allow cck tx 19:18 r/w gf20_prot_nav txop protection type for gf20 tx 0: none 1: short nav protection 2: long nav protection 3: reserved (none) 0 17:16 r/w gf20_prot_ctrl protection control frame type for gf20 tx 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 0 15:0 r/w gf20_prot_rate protection control frame rate for g f20 tx (including rts/cts - to - self/cf - end) default: ofdm 24m 0x4004 gf40_prot_cfg: gf40_prot_cfg register (offset: 0x1378) bits type name description initial value 31:27 - - reserved 0 26 r/w gf40_rtsth_en rts thr eshold enable on gf40 tx 0: disable 1: en able 0 25:20 r/w gf40_prot_txop gf40 txop allowance (0: disallow, 1: allow) bit25: allow gf - 40 tx bit24: allow gf - 20 tx bit23: allow mm - 40 tx bit22: allow mm - 20 tx bit21: allow ofdm tx bit20: allow cck tx 16 19:18 r/w gf40_prot_nav txop protection type for gf40 tx 0: none 1: short nav protection 2: long nav protection 3: reserved (none) 0 17:16 r/w gf40_prot_ctrl protection control frame type for gf40 tx 0: none 1: rts/cts 2: cts - to - self 3: reserved (none) 0 15:0 r/w gf40_prot_rate protection control f rame rate for gf40 tx (including rts/cts - to - self/cf - end) default: duplicate ofdm 24m 0x4084 exp_cts_time: exp_cts_time register (offset: 0x137c) bits type name description initial value 31 - - reserved 0 30:16 r/w exp_ofdm_cts_ time expected time for of dm cts response (unit: 1us) 56 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 212 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years used for outgoing nav setting. default: sifs + 6mbps cts 15 r - reserved 0 14:0 r/w exp_cck_cts_tim e expected time for cck cts r esponse (unit: 1us) used for outgoing nav setting. default: sifs + 1mbps cts 314 exp_ack_t ime: exp_ack_time register (offset: 0x1380) bits type name description initial value 31 - - reserved 0 30:16 r/w exp_ofdm_ack_t ime expected time for ofdm ack response (unit: 1us) used for outgoing nav setting. default: sifs + 6mbps ack preamble 36 15 - - reserved 0 14:0 r/w exp_cck_ack_tim e expected time for ofdm ack response (unit: 1us) used for outgoing nav setting. default: sifs + 1mbps ack preamble 202 3.20.3.6 mac rx configuration registers (base: 1018.0000) rx_filtr_cfg: rx_filtr_cfg register (offset: 0x1400) bits type name description initial value 31:17 - - reserved 0 16 r/w drop_ctrl_rsv drop reserve control subtype 1 15 r/w drop_bar drop bar 0 14 r/w drop_ba drop ba 1 13 r/w drop_pspoll drop ps - poll 0 12 r/w drop_rts drop rts 1 11 r/w drop_c ts drop cts 1 10 r/w drop_ack drop ack 1 9 r/w drop_cfend drop cf - end 1 8 r/w drop_cfack drop cf - end + cf - ack 1 7 r/w drop_dupl drop duplicated frame 1 6 r/w drop_bc drop broadcast frame 0 5 r/w drop_mc drop multicast frame 0 4 r/w drop_ver_err drop 802.11 version error frame 1 3 r/w drop_no t_mybss drop frame that is not my bssid 1 2 r/w drop_uc_nome drop not to me unicast frame 1 1 r/w drop_phy_err drop physical error frame 1 0 r/w drop_crc_err drop crc error frame 1 note: 1 : enable, 0: disable . auto_rsp_cfg: auto _rsp _cfg register (offset: 0x1404) bits type name description initial value 31:8 - - reserved 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 213 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 7 r/w ctrl_pwr_bit power bit value in control frame 0 6 r/w bac_ack_policy ba frame - > bac - > ack policy bit value 0 5 - - reserved 0 4 r/w cck_short_en cck short preamble auto response enable 0: disable 1: enable 0 3 r/w cts_40m_ref in duplicate legacy cts response mode, refer to extension cca to decide duplicate or not. 0: disable 1: enable 0 2 r/w cts_40m_mode duplicate legacy cts response mode 0: disable 1: enable 0 1 r/w bac_ackpolicy_en bac ack policy bit enable 0: disable; dont care this bit 1: enable; no ba auto responding upon reception of bar with no ack policy 1 0 r/w auto_rsp_en auto r esponder enable 1 legacy_basic_ra te: legacy_basic_rate register (offset: 0x1408) bits type name description initial value 31: 12 - - reserved 0 11: 0 r/w legacy_basic_rate legacy basic rate bit mask bit0: 1 mbps is basic rate bit1: 2 mbps is basic rate bit2: 5.5 mbps is basic rate bit3 : 11 mbps is basic rate bit4: 6 mbps is basic rate bit5: 9 mbps is basic rate bit6: 12 mbps is basic rate bit7: 18 mbps is basic rate bit8: 24 mbps is basic rate bit9: 36 mbps is basic rate bit10: 48 mbps is basic rate bit11: 54 mbps is basic rate 0: disa ble 1: enable 0 ht_basic_rate: ht_basic_rate register (offset: 0x140c) bits type name description initial value 31: 16 r/w - reserved 0 15: 0 r/w ht_basic_rate ht basic rate for auto responding control frame bit15 =1, enable mcs feedback 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 214 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ht_ctrl_c fg: ht_ctrl_cfg register (offset: 0x1410) bits type name description initial value 31: 9 - - reserved 0 8: 0 r/w ht_ctrl_thres remaining txop threshold for ht control frame auto responding (unit: us) 256 sifs_cost_cfg: sifs_cost_cfg register (offset: 0 x1414) bits type name description initial value 31:16 - - reserved 0 15:8 r/w ofdm_sifs_cost ofdm sifs time (unit: 1us) applied after ofdm tx/rx. 16 7:0 r/w cck_sifs_cost cck sifs time (unit: 1us) applied after cck tx/rx. 10 note: the ofdm_sifs_cost and cck_sifs_cost are used only for duration field calculation. it will not affect the responding timing. rx_parser_cfg: rx_parser_cfg register (offset: 0x1418) bits type name description initial value 31:16 - - reserved 0 0 r/w nav_all_en set nav for al l received frames 0: disable (unicast to me frame will not set the nav) 1: enable 0 3.20.3.7 mac security configuration registers (base: 1018.0000) tx_sec_cnt0: tx_sec_cnt0 register (offset: 0x1500) bits type name description initial value 31:16 rc tx_sec_err_cn t tx sec packet error count 0 15:0 rc tx_sec_cpl_cnt tx sec packet complete count 0 rx_sec_cnt0 : rx_sec_cnt0 register (offset: 0x1504) bits type name description initial value 31:16 - - reserved 0 15:0 rc rx_sec_cpl_cnt rx sec packet complete count 0 ccmp_fc_mute: ccmp_fc_mute register (offset: 0x1508) bits type name description initial value 31:16 r/w ht_ccmp_fc_mute ht rate ccmp fc mute 0xc78f 15:0 r/w lg_ccmp_fc_mute legacy rate ccmp fc mute 0xc78f 3.20.3.8 mac hcca/psmp csr (base: 1018.0000) txop_hldr_ad dr0 : txop_hldr_addr0 register (offset: 0x1600) bits type name description initial value 31:24 r/w txop_ho l_3 txop holder mac address byte3 0 23:16 r/w txop_ho l_2 txop holder mac address byte2 0 15:8 r/w txop_ho l_1 txop holder mac address byte1 0 7:0 r/ w txop_ho l_0 txop holder mac address byte0 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 215 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years txop_hldr_addr1 : txop_hldr_addr1 register (offset: 0x1604) bits type name description initial value 31:16 - - reserved 0 15:8 r/w txop_ho l_5 txop holder mac address byte5 0 7:0 r/w txop_ho l_4 txop holder ma c address byte4 0 note: byte0 is the first byte on network. its lsb bit is the first bit on network. for a mac address captured on the network with order 00:01:02:03:04:05, byte0=00, byte1 =01 etc. txop_hldr_et: txop_hldr_et register (offset:0x1608) bits t ype name description initial value 31:26 - - reserved 0 25 r/w txop_etm1 _en txop holder early termination interrupt enable (type 1) upon the reception of qos data frame from txop_hldr_addr (a2) and queue size (qs) in qos control field (qc) is equal to z ero, txop holder early termination interrupt will be issue. 0: disable 1: enable 0 24 r/w txop_etm0 _en txop holder early termination interrupt enable (type 0) when rx packet is from txop holder specified in qos_csr0,1 (match with addr2) and duration v alue is less than or equal to early termination duration threshold specified below, txop holder early termination interrupt will be issued after crc check is upon the reception of qos data frame from txop_hldr_addr (a2) and duration (dur) is less th an or equal to early termination duration threshold (txop_etm_thres), txop holder early termination interrupt will be issue. unit: 1usec 0 15:9 - - reserved 0 8 wc txop_eto_en txop holder early timeout enable write 1 to enable early timeout check. (interrupt when timeout) when enabled, hardware will expect cca event. if hardware didnt sense cca over the txop holder txop holder early timeout interrupt will then be unit: 1usec 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 216 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0 r/w per_rx_rst_en baseband rx_pe per rx reset enable 0: disable, 1: enable 0 note1: txop holder early timeout inter rupt (txop_eto _int) is used by ap for hc purpose. note2: txop holder early termination interrupt (txop_etm_int) is used by sta (both ap and non - ap sta) for hc purpose. qos_cfpoll_ra_dw0: qos_cfpo ll_ra_dw0 register (offset: 0x160c) bits type name descriptio n initial value 31:24 r cfpoll_a1_byte3 byte3 of a1 of received qos data (+) cf - poll frame x 23:16 r cfpoll_a1_byte2 byte2 of a1 of received qos data (+) cf - poll frame x 15:8 r cfpoll_a1_byte1 byte1 of a1 of received qos data (+) cf - poll frame x 7:0 r cfpoll_a1_byte0 byte0 of a1 of received qos data (+) cf - poll frame x qos_cfpoll_a1 _dw1: qos_cfpoll_ra_dw1 register (offset: 0x1610) bits type name description initial value 31:24 - - reserved 0 16 r cfpoll_a1_to me 1: qos cf - poll to me 0: qos cf - poll not to me x 15:8 r cfpoll_a1_byte5 byte5 of a1 of received qos data (+) cf - poll frame x 7:0 r cfpoll_a1_byte4 byte4 of a1 of received qos data (+) cf - poll frame x qos_cfpoll_qc: qos_cfpoll_qc register (offset: 0x1614) bits type name description initial val ue 31:24 - - reserved 0 15:8 r cfpoll_qc_byte1 byte1 of qc of received qos data (+) cf - poll frame x 7:0 r cfpoll_qc_byte0 byte0 of qc of received qos data (+) cf - poll frame x note: cfpoll_ra_dw0, cfpoll_ra_dw1, and cfpoll_qc are updated after the rec ep tion of qos data (+) cf - poll frame and rx qos cf - poll interrupt (rx_qos_cfpo ll_int) is launched then 3.20.3.9 mac statistic counters (base: 1018.0000) rx_sta_cnt0: rx_sta_cnt0 register (offset: 0x1700) bits type name description initial value 31:16 rc phy_errcnt r x phy error frame count 0 15:0 rc crc_errcnt rx crc error frame count 0 note1: rx phy error means psdu length is shorter than indicated by plcp. note2: rx phy error is also treated as crc error. rx_sta_cnt1: rx_sta_cnt1 register (offset: 0x1704) bits typ e name description initial value 31:16 rc plpc_errcnt rx plcp error count 0 15:0 rc cca_errcnt cca false alarm count 0 note1: cca false alarm means there is no plcp after cca indication. note2: rx plcp error means there is no psdu after plcp indication. rx_sta_cnt2: rx_sta_cnt2 register (offset: 0x1708) bits type name description initial value 31:16 rc rx_ovfl_cnt rx fifo overflow frame count 0 15:0 rc rx_dupl_cnt rx duplicated filtered frame count 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 217 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years note: mac will not auto respond ack/ba to the frame originator when frame is lost due to rxfifo overflow. however, mac will respond when frame is duplicated filtered. tx_sta_cnt0 : tx_sta_cnt0 register (offset: 0x170c) bits type name description initial value 31:16 rc tx_bcn_cnt tx beacon count 0 15:0 rc tx_fail_cnt failed tx count 0 tx_sta_cnt1 : tx_sta_cnt1 register (offset: 0x1710) bits type name description initial value 31:16 rc tx_rty_cnt tx retransmission count 0 15:0 rc tx_succ_cnt successful tx count 0 tx_sta_cnt2 : tx_sta_cnt2 register (offset: 0x1714) bits type name description initial value 31:16 rc tx_udfl_cnt tx underflow count 0 15:0 rc tx_zero _cnt tx zero length frame count 0 tx_stat_fifo: tx_stat_fifo register (offset: 0x1718) bits type name description initial value 31:16 r txq_rate tx success rate * 15:8 r txq_wcid tx wcid * 7 r txq_ackreq tx acknowledge required 0: not required 1: required * 6 r txq_agg tx aggregate 0: non - aggregated 1: aggregated * 5 r txq_ok tx success 0: failed 1: success * 4:1 r txq_pid tx packet id (latche d from txwi) * 0 rc txq_vld tx status queue valid 0: queue empty, 1: valid 0 note: tx status fifo size = 16. tx_nag_agg_cnt: tx_nag_agg_cnt register (offset: 0x171c) bits type name description initial value 31:16 rc tx_agg_cnt aggr egate tx count 0 15:0 rc tx_nag_cnt non - aggregate tx count 0 tx_agg_cnt0 : tx_agg_cnt0 register (offset: 0x1720) bits type name description initial value 31:16 rc tx_agg_2 _cnt aggr egate size = 2 mpdu count 0 15:0 rc tx_agg_1 _cnt aggr egate size = 1 mpdu count 0 tx_agg_cnt1 : tx_agg_cnt1 register (offset: 0x1724) bits type name description initial value 31:16 rc tx_agg_4 _cnt aggr egate size = 4 mpdu count 0 15:0 rc tx_agg_3 _cnt aggr egate size = 3 mpdu count 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 218 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years tx_agg_cnt2 : tx_agg_cnt2 register (offset: 0x1728) bits type name description initial value 31:16 rc tx_agg_6 _cnt aggr egate size = 6 mpdu count 0 15:0 rc tx_agg_5 _cnt aggr egate size = 5 mpdu count 0 tx_agg_cnt3 : tx_agg_cnt3 register (offset: 0x172c) bits type name description initial value 31:16 rc tx_agg_8 _cnt aggr e gate size = 8 mpdu count 0 15:0 rc tx_agg_7 _cnt aggr egate size = 7 mpdu count 0 tx_agg_cnt4 : tx_agg_cnt4 register (offset: 0x1730) bits type name description initial value 31:16 rc tx_agg_10_cnt aggr egate size = 10 mpdu count 0 15:0 rc tx_agg_9 _cnt agg r egate size = 9 mpdu count 0 tx_agg_cnt5 : tx_agg_cnt5 register (offset: 0x1734) bits type name description initial value 31:16 rc tx_agg_12_cnt aggr egate size = 12 mpdu count 0 15:0 rc tx_agg_11_cnt aggr egate size = 11 mpdu count 0 tx_agg_cnt6 : tx_agg_ cnt6 register (offset: 0x1738) bits type name description initial value 31:16 rc tx_agg_14_cnt aggr egate size = 14 mpdu count 0 15:0 rc tx_agg_13_cnt aggr egate size = 13 mpdu count 0 tx_agg_cnt7 : tx_agg_cnt7 register (offset: 0x173c) bits type name desc ription initial value 31:16 rc tx_agg_16_cnt aggr egate size > 16 mpdu count 0 15:0 rc tx_agg_15_cnt aggr egate size = 15 mpdu count 0 mpdu_density_cnt: mpdu_density_cnt register (offset: 0x1740) bits type name description initial value 31:16 rc rx_zero_ del_cnt rx zero length delimiter count 0 15:0 rc tx_zero _del_cnt tx zero length delimiter count 0 3.20.3.10 mac search table (base: 0x1018.0000) rx_wc_sef: rx wcid search entry format (8 bytes) offset type name description initial value 0x00 r/w wc_mac_addr0 clie nt mac address byte0 0x00 0x01 r/w wc_mac_addr1 client mac address byte1 0x00 0x02 r/w wc_mac_addr2 client mac address byte2 0x00 0x03 r/w wc_mac_addr3 client mac address byte3 0x00 0x04 r/w wc_mac_addr4 client mac address byte4 0x00 0x05 r/w wc_mac_a ddr5 client mac address byte5 0x00 0x06 r/w ba_sess_mask0 ba session mask (lower) bit0 for tid0 bit7 for tid7 0x00 0x07 r/w ba_sess_mask1 ba session mask (upper) 0x00 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 219 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years bit8 for tid8 bit15 for tid15 rx_wc_st: rx wcid search table (offset: 0x1800) offset t ype name description initial value 0x1800 r/w wc_entry_0 wc mac address with wcid=0 0 0x1808 r/w wc_entry_1 wc mac address with wcid=1 0 . . note1: wcid=wireless client id. 3.20.3.11 security table/cis/beacon/null frame (base : 0x1018.0000, offset: 0x4000) skf: security key format (8dw) offset type name description initial value 0x00 r/w seckey_dw0 security key by te3~0 * 0x04 r/w seckey_dw1 security key byte7~4 * 0x08 r/w seckey_dw2 security key byte11~8 * 0x0c r/w seckey_dw3 security key byte15~12 * 0x10 r/w txmic_dw0 tx mic key byte3 ~0 * 0x14 r/w txmic_dw1 tx mic key byte7 ~4 * 0x18 r/w rxmic_dw0 rx mic key byte3~0 * 0x1c r/w rxmic_dw1 rx mic key byte7~4 * note: 1. for wep40, ckip40, only byte4~0 of security key are valid. 2. for wep104, ckip104, only byte12~0 of security key are valid. 3. for tkip, aes, all the bytes of security key are valid. 4. tx/rx mic key is used only for tkip mic calculation. iv/eiv _f: iv/eiv format (2 dw) when txinfo.wiv=0, hardware will auto lookup iv/eiv from this table and update iv/eiv after encryption is finished. offset type name description initial value 0x00 r/w iv_fieled i v field * 0x04 r/w eiv_fieled eiv field * note1: the key index and extension iv bit shall be initialized by software. the msb octet of iv will not be modified by hardware note2: iv/eiv packet number (pn) counter modes: a. for wep40, wep104, ckip40, ckip104, ckip128 mode, pn=iv[23:0]. eiv[31:0] is not used. b. for tkip mode, pn = {eiv[31:0], iv[7 :0], iv[23:16]}, iv[15:8]=(iv[7:0] | 0x20) & 0x7f) is generated by hardware. c. for aes - ccmp, pn = {eiv[31:0], iv[15:0] } d. pn = pn + 1 after each encryption. note3: software may initialize the pn counter to any value. wcid_aef: wcid attribute entry format (1dw) offset type name description initial value 31:10 - - reserved * 9:7 r/w rxwi_udf rxwi user define field this field is tagged in the rxwi.udf fields for the * free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 220 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years wcid. 6:4 r/w bss_idx multiple - bss index for the wcid * 3:1 r/w rx_pkey_mode pair - wise key security mode 0: no security 1: wep40 2: wep104 3: tkip 4: aes - ccmp 5: ckip40 6: ckip104 7: ckip128 * 0 r/w rx_pkey_en key table selection 0: shared key table 1: pair - wise key table * skme: share key mode entry format (1dw) bits type name description initial value 31 - - reserved * 30:28 r/w skey_mode_7 + shared key7+(8x) mode, x =0~3 * 27 - - reserved * 26:24 r/w skey_mode_6 + shared key6+(8x) mode, x =0~3 * 23 - - reserved * 22:20 r/w skey_mode_5 + shared key5+(8x) mode, x =0~3 * 19 - - reserved * 18:16 r/w skey_mode_4 + shared key4+(8x) mode, x =0~3 * 15 - - reserved * 14:12 r/w skey_mode_3 + shared key3+(8x) mode, x =0~3 * 11 - - reserved * 10:8 r/w skey_mode_2 + shared key2+(8x) mode, x =0~3 * 7 - - reserved * 6:4 r/w skey_mode_1 + shared key1+(8x) mode, x =0~3 * 3 - - reserved * 2:0 r/w skey_mode_0 + shared key0+(8x) mode, x =0~3 * key mode definition: 0: no security 1: wep40 2: wep104 3: tkip 4: aes - ccmp 5: cki p40 6: ckip104 7: ckip128 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 221 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.12 security table pwkt: pair - wise key table (offset: 0x4000) offset type name description initial value 0x4000 r/w pkey_0 pair - wise key for wcid0 * 0x4020 r/w pkey_1 pair - wise key for wcid1 * . . . . . . free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 222 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 0x6e40 r/w skey_18 shared key for bss_idx=4, key_idx=2 * 0x6e60 r/w skey_19 shared key for bss_idx=4, key_idx=3 * 0x6e80 r/w skey_20 shared key for bss_idx=5, key_idx=0 * 0x6e a0 r/w skey_21 shared key for bss_idx=5, key_idx=1 * 0x6ec0 r/w skey_22 shared key for bss_idx=5, key_idx=2 * 0x6ee0 r/w skey_23 shared key for bss_idx=5, key_idx=3 * 0x6f00 r/w skey_24 shared key for bss_idx=6, key_idx=0 * 0x6f20 r/w skey_25 shared ke y for bss_idx=6, key_idx=1 * 0x6f40 r/w skey_26 shared key for bss_idx=6, key_idx=2 * 0x6f60 r/w skey_27 shared key for bss_idx=6, key_idx=3 * 0x6f80 r/w skey_28 shared key for bss_idx=7, key_idx=0 * 0x6fa0 r/w skey_29 shared key for bss_idx=7, key_idx =1 * 0x6fc0 r/w skey_30 shared key for bss_idx=7, key_idx=2 * 0x6fe0 r/w skey_31 shared key for bss_idx=7, key_idx=3 * skm: shared key mode (offset: 0x7000) offset type name description initial value 0x7000 r/w skey_mode_0 _7 shared mode for skey0 - skey7 * 0x7004 r/w skey_mode_8 _15 shared mode for skey8 - skey15 * 0x7008 r/w skey_mode_16_23 shared mode forskey16 - skey23 * 0x700c r/w skey_mode_24_31 shared mode for skey24 - skey31 * free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 223 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.13 descriptor and wireless information 3.20.3.13.1 tx frame informa tion to transmit a frame, the driver needs to prepare the tx frame information for hardware. the tx frame information contains the transmission control, the header, and the payload. the transmission control information (the txwi ) is used by the mac and b bp and is applied for the associated tx frame when transmission. the header and payload is the content of an 802.11 packet. the tx information could be scattered in several segments. the tx descriptor (the txd ) specifies the location and length of the tx frame information segment. tx frame information could be linked by use of several txd. these txd are arranged in a txd ring in serial. below diagram illustrates the linking between txd and tx frame information. fig. 3 - 20 - 3 tx frame information txd(0) sdp0 sdl0, ls0 = 0 txd(0) sdp1 sdl1, ls1 = 0 txwi(4dw) 802.11 header tx payload (segment 0) tx payload (segment 1) tx payload (segment n) txd(1) sdp0 sdl0, ls0 = 0 txd(1) sdp1 sdl1, ls1 = 0 txd(k) sdp0 sdl0, ls0 = 0 txd(k) sdp1 sdl1, ls1 = 1 txd(0).sdp0 txd(0).sdp1 txd(1).sdp0 txd(k).sdp1 txd ring txd for tx frame i free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 224 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.13.2 tx descriptor format fig. 3 - 20 - 4 tx descriptor format ? sdp0 : segment data pointer 0 ? sdl0 : segment data length for the data pointed by sdp0. ? sdp1 : segment data pointer 1. ? sdl1 : s egment data length for the data pointed by sdp1. ? ls0 : data pointed by sdp0 is the last segment ? ls1 : data pointed by sdp1 is the last segment ? ddone : dma done. dma has transferred the segments pointed by this tx descriptor 3.20.3.13.3 txwi format fig. 3 - 20 - 5 txwi format ? frag : 1: to inform tkip engine this is a fragment, so that tkip mic is appended by driver at the last fragment; hardware tkip engine only need to insert iv/eiv and icv sdp0[31:0] sdl0[13:0] d d o n e l s 0 sdl1[13:0] b u r s t l s 1 sdp1[31:0] qsel w i v rsv[23:0] rsv[4:0] bit 31 bit 0 mpdu total byte count[11:0] t s a m p d u c f a c k mcs[6:0] mpdu desity [2:0] m i m o o f d m m m p s tx packet id[3:0] f r a g iv [31:0] eiv [31:0] wcid[7:0] bawinsize[5:0] n s e q a c k b w s g i stb c reserved [2:0] reserved[5:0] txo p [1:0] bit 31 bit 0 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 225 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? mmps : 1 : the rem ote peer is in dynamic mimo - ps mode ? cfack : 1: if an ack is required to the same peer as this outgoing data frame, then mac tx will send a single data+cfack frame instead of separate ack and data frames. 0: no piggyback ack allowed for the ra of this frame. ? ts : 1: this is a beaco n or proberesponse frame and mac needs to auto insert 8 - byte timestamp after 802.11 wlan header. ? ampdu : this frame is eligible for ampdu. mac tx will aggregate subsequent outgoing frames having whenever txop allows. even ther es only one data frame to be sent, as long as the ampdu bit in txwi is on, mac will still package it as ampdu with implicit bar. this adds only 4 - byte ampdu delimiter overhead into the outgoing frame and imply the response frame is a ba instead of ack. no te: driver should set ampdu=1 only after a ba session is successfully negotiated, because block ack is the only way to acknowledge in ampdu case. ? mpdu density : 1/4usec ~ 16usec per - peer parameter used in outgoing a - mpdu. (this field complies with the minimum mdpu starting spacing of the a - mpdu parameter field of draft 1.08). 000 - no restriction 001 - 1/4 sec 010 - 1/2 sec 011 - 1 sec 100 - 2 se 101 - 4 sec 110 - 8 sec 111 - 16 sec ? txop: tx back off mode. 0 : ht txop rule; 1: pifs tx ; 2: sifs (only when previous frame exchange is successful); 3: back off. ? mcs/bw/shortgi/ofdm/ mimo : tx data rate & mimo parameters for this outgoing frame to be filled into bbp. ? ack : this bit informs mac to wait for ack or not after transmission of t he frame. event though qod data frame has ack policy in its qos control field, mac tx solely depends on this ack bit to decide waiting of ack or not. ? nseq : 1: to use the special h/w seq number register in mac block. ? ba window size: tell mac the maximum nu mber of to - be - baed frames is allowed of the ra (ras ba re - ordering buffer size) ? wcid (wireless client index) : lookup result of addr1 in the peer table (255=not found). this index is also used to find all the attributes of the wireless peer (e.g. tx rate, tx power, pair - wise key, iv, eiv,). this index has consistent meaning in both driver and hardware. ? msdu total byte count : total length of this frame . ? packet id: as a cookie specified by driver and will be latched into the tx r esult register stack. driver use this field to identify special frames tx result. ? iv : used by encryption engine. ? eiv: used by encryption engine. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 226 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.13.4 rx descriptor ring the rx descriptor (the rxd ) specifies the location to place the payload of the received frame (the rx payload) an d the associated receiving information (the rxwi ). one rxd serves for one receiving frame. only sdp0 and sdl0 are useful in the rxd. the rxd is arranged in the rxd ring in serial. the hardware links the rxwi and rx payload in serial and place it to the l ocation specified in sdp0. see below diagram. fig. 3 - 20 - 6 rx descriptor ring 3.20.3.13.5 rx descriptor format fig. 3 - 20 - 7 rx descriptor format rxd(0) sdp0 sdl0, ls0 rxd(0) sdp1 sdl1, ls1 rxwi(4dw) rx payload rxd(1) sdp0 sdl0, ls0 rxd(1) sdp1 sdl1, ls1 rxd(0).sdp0 rxd ring rxd for rx frame i rxd for rx frame i+1 rxwi(4dw) rx payload rxd(1).sdp0 rxd(2) sdp0 sdl0, ls0 rxd(2) sdp1 sdl1, ls1 rxd for rx frame i+2 sdp0[31:0] d d o n e l s 0 sdl1[13:0] 0 1 sdp1[31:0] a m p d u 15'b0 bit 31 bit 0 l 2 p a d r s s i h t c a m s d u m i c e r r i c v e r r c r c e r r m y b s s b c m c u c 2 m e f r a g n u l l d a t a b a sdl0[13:0] d e c free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 227 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years following fields are driver - specified. ? sdp0 : segment data pointer 0. ? sdl0 : segment data length for the data pointed by sdp0. ? sdp1 : segment data pointer 1. ? sdl1 : segment data length for the data pointed by sdp1. ? ddone : dma done. dma has moved the rx frame to the speci fied location. set by hardware and cleared by driver. following fields are filled by hardware. ? ba : the r eceived frame is part of ba session, need to do re - ordering. ? data : 1: the r eceived frame is data type. ? null : 1: the received frame has sub - type null/qo s - null. ? frag : 1: the r eceive frame is a fragment ? uc2me : 1: the received frame addr1 = my mac address ? mc : 1: the received frame addr1 = multicast ? bc : 1: the r eceived frame addr1 = ff:ff:ff:ff:ff:ff ? mybss : 1 : the received frame bssid is one of my bss (as an ap, max 4 bssid supported) ? crc error : 1: the rec eived frame is crc error ? icv error : 1: the rec eived frame is icv error ? mic error : 1: the received frame is mic error (rx cnrl register should support individual pass - up error frame to driver in order to imple ment mic error detection feature) ? amsdu : the received frame is in a - msdu sub frame format which is <802.3 + msdu + padding> ? htc : 1: this received frame came with htc field, 0: no htc field ? rssi : 1: rssi information available in rssi0, rssi1, rssi2 fields ? l 2pad : 1: the l2 header is recognizable and been 2 - byte - padded to ensure payload to align at 4 - byte boundary. 0: l2 header not extra padded ? ampdu : 1: this is an ampdu segr egated frame ? dec : 1 : this is a decrypted frame 3.20.3.13.6 rxwi format fig. 3 - 20 - 8 rxwi format tid [3:0] wcid[7:0] udf [2:0] mpdu total byte count[11:0] bss idx [2:0] key idx [1:0] bit 31 bit 0 rsv[15:0] snr_0[7:0] snr_1[7:0] fn[3:0] stbc [1:0] s g i b w sn[11:0] mcs[6:0] phy mode [1:0] rsv [2:0] rsv[7:0] rssi_0[7:0] rssi_1[7:0] rssi_2[7:0] free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 228 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years ? wcid : index of addr2 in the pair wise key table. this value uniquely identifies the ta. wcid=255 means not found. ? key index : 0~3 ex tracted from iv field. for driver reference only, no particular usage so far. ? bssid index : 0 ~7 f or bssid0~7. extract from 802.11 header (the last three bits of bssid field) ? udf : user defined field. ? mpdu total byte count : the entire mpdu length. ? tid : extracted from 8002.11 qos control field. ? fn : fragment number of the received mpdu. extract from 802.1 1 header. ? sn : sequenc e number of the r eceived mpdu. used for ba re - ordering especially that amsdu are auto segregated by hardware and lost the 802.11 header. ? mcs/bw/sgi/phymode : rx data rate & related mimo parameters of this frame got from plcp header. see next section for the detail. ? rssi0 , rssi1, rssi2 : bbp reported rssi information of the received frame. ? snr0, snr1 : bbp reported snr information of the received frame. 3.20.3.13.7 brief phy rate format and definition a 16 - bit brief phy rate is used in mac hardware . it is the same phy rate field described in txwi and rxwi. bit name description 15:14 phy mode preamble mode 0: legacy cck, 1: legacy ofdm, 2: ht mix mode, 3 : ht green field 13:11 - reserved 10:9 - reserved 8 sgi short guard interval, only support for ht mode 0: 800ns, 1: 400ns 7 bw bandwidth support both legacy and ht modes 40mhz in legacy mode means duplicate legacy 0: 20mhz, 1: 40mhz 6:0 mcs modulation coding scheme table. brief phy rate format mode = legacy cck mcs = 0 long preamble cck 1mbps mcs = 1 long preamble cck 2mbps mcs = 2 long preamble cck 5.5mbps mcs = 3 long preamble cck 11mbps mcs = 8 short preamble cck 1mbps * illegal rate mcs = 9 short preamble cck 2mbps mcs = 10 short preamble 5.5mbps mcs = 11 short preamble 11mbps othe r mcs codes are reserved in legacy cck mode. bw and sgi are reserved in legacy cck mode. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 229 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years mode = legacy ofdm mcs = 0 6mbps mcs = 1 9mbps mcs = 2 12mbps mcs = 3 18mbps mcs = 4 24mbps mcs = 5 36mbps mcs = 6 48mbps mcs = 7 54mbps other mcs code in le gacy cck mode are reserved when bw = 1, duplicate legacy ofdm is sent. sgi is reserved in legacy ofdm mode. mode = ht mix mode / ht green field mcs = 0 (1s) (bw=0, sgi=0) 6.5 mbps mcs = 1 (bw=0, sgi=0) 13mbps mcs = 2 (bw=0, sgi=0) 19.5mbps mcs = 3 (bw =0, sgi=0) 26mbps mcs = 4 (bw=0, sgi=0) 39mbps mcs = 5 (bw=0, sgi=0) 52mbps mcs = 6 (bw=0, sgi=0) 58.5mbps mcs = 7 (bw=0, sgi=0) 65mbps mcs = 8 (2s) (bw=0, sgi=0) 13mbps mcs = 9 (bw=0, sgi=0) 26mbps mcs = 10 (bw=0, sgi=0) 39mbps mcs = 11 (bw=0, sg i=0) 52mbps mcs = 12 (bw=0, sgi=0) 78mbps mcs = 13 (bw=0, sgi=0) 104mbps mcs = 14 (bw=0, sgi=0) 117mbps mcs = 15 (bw=0, sgi=0) 130mbps mcs = 32 (bw=1, sgi=0) ht duplicate 6mbps when bw=1, phy_rate = phy_rate * 2 when sgi=1, phy_rate = phy_rate * 10/9 the effects of bw and sgi are accumulative. when mcs=0~7(1s), sgi option is supported. bw option is supported. when mcs=8~15(2s), sgi option is supported. bw option is supported. when mcs=32, only sgi option is supported. bw option is not supported. (bw = 1) other mcs code in ht mode are reserved free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 230 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.14 driver implementation note 3.20.3.14.1 nstruction of down load 8051 firmware 1. select on - chip program memory i. sys_ctrl.hst_pm_sel (0x0400.bit[16]) =1 2. write firmware into program memory space, which starts at 0x2000. 3. close on - chi p program memory. i. sys_ctrl.hst_pm_sel (0x0400.bit[16]) =0 4. 8051 starts 3.20.3.14.2 instruction of initialize dma 1. set base addresses and total number of descriptors: i. tx_base_ptr0~tx_base_ptr5 ii. rx_base_ptr iii. tx_max_cnt0~tx_max_cnt iv. rx_max_cnt 2. set w mm parameters i. wmm_aifsn_cfg ii. wmm_cw min_cfg iii. wmm_cw max_cfg iv. wmm_txop0_cfg and wmm_txop1_cfg 3. set dma global configuration except tx_dma_en and rx_dma_en bits: i. wpdma_glo_cfg 4. set interrupt configuration: i. delay_int_cfg 5. enable dma interrupt: i. int_mask 6. enable dma: i. wpdma_glo_cfg.tx_dma_en = 1 wpdma_glo _cfg.rx_dma_en = 1 3.20.3.14.3 instruction of clock control 3.20.3.14.3.1 clock turn - off sequence 1. switch 80mhz main clock to pll clock: i. set sys_ctrl.clkselect = 1 2. turn clock off: i. set sys_ctrl.mac_clk_en = 0 ii.set sys_ctrl.dma_clk_en = 0 3. tu rn off pll: i. set pwr_pin_cfg.io_pll_pd = 1. 3.20.3.14.3.2 clock turn - on sequence 1. turn on pll: i. set pwr_pin_cfg.io_pll_pd = 0 2. waiting at least $bbp_pll_ready for pll clock stable: 3. turn on clock: i. set sys_ctrl.mac_clk_en = 1 ii. set sys_ctrl.dma_clk_en = 1 free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 231 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.14.4 instruction of tx/r x control 3.20.3.14.4.1 freeze tx and rx sequence 1. disable dma tx: i. set wpdma_glo_cfg..tx_dma_en = 0 2. polling until dma tx becomes idle and pbf tx queue becomes empty: i. polling wpdma_glo _cfg. tx_dma_busy = 0 ii. polling txrxq_sta.tx0q_sta = 2, txrxq_sta.tx1q_sta = 2, pollin g txrxq_sta.tx2q_sta = 2. iii. if the polling period > $dma_tx _polling_timeout, abort power saving procedure. 3. disable mac tx and rx: i. set mac_sys_ctrl.mac_rx_en = 0 ii. mac_sys_ctrl.mac_tx_en = 0 4. polling until mac tx and rx is disabled: i. polling mac_status_r eg. tx_status = 0, mac_status_reg. rx_status = 0 ii. if the polling period > $mac_polling_timeout, abort power saving procedure. 5. disable dma rx: i. set wpdma_glo_cfg..rx_dma_en = 0 . 6. polling until both dma rx becomes idle and pbf rx queue becomes empty: i. pol ling wpdma_glo _cfg. rx_dma_busy =0. ii. polling txrxq_sta.rx0q_sta = 0x22. iii. if the polling period > $dma_rx_polling_timeout, abort power saving procedure. 3.20.3.14.4.2 recover tx and rx sequence 1. enable dma tx and rx: i. set wpdma_glo_cfg..rx_dma_en = 1 ii. set wpdma_glo_cfg..tx_dm a_en = 1 2. enable mac tx and rx: i. set mac_sys_ctrl.mac_rx_en = 1 ii. set mac_sys_ctrl.mac_tx_en = 1 3.20.3.14.5 instruction of rf power on/off sequence 1. power down rf components sequence i. power down rf component 2. set pwr_pin_cfg.io_adda_pd = 1. 3. set pwr_pin_cfg.io_rf_pe = 0. 4. set tx_pin_cfg.trsw_en = 0. 5. set tx_pin_cfg.rftr_en = 0 . 6. set tx_pin_cfg.lna_pe*en = 0. 7. set tx_pin_cfg.pa_pe*en = 0. 8. enable rf components sequence i. recover the registers in previous sequence. ii. wait $rf_pll_ready for rf pll becomes stable. 3.20.3.14.6 power saving procedure 1. freeze tx and rx 2. power down led and rf components 3. clock turn - off free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 232 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 3.20.3.14.7 power recovery procedure 1. clock turn - on 2. enable led and rf components 3. recover tx and rx 3.20.3.14.8 parameters 1. $rf_pll_ready = tbd. 2. $bbp_pll_ready = 500 us. 3. $dma_rx_polling_timeout = tbd. 4. $dma_tx_polling _timeout = tbd. 5. $mac_polling_timeout = tbd. free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 233 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 4. package physical dimension 4.1 tfbga 289 b free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 234 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years free datasheet http://www.datasheetlist.com/
RT3050/52 datasheet preliminary re vision august 14, 2008 ds r 3050/52 _ v.2.0_081408 - 235 - form no. qs - 073 - f02 rev. 1 kept by dcc ret. t ime 5 years 5. revision history rev date from description 2 .0 2008/ 8 /1 4 frank lu initial release this product i s not designed for use in medical, life support applications. do not use this product in these types of equipments or applications .this document is subject to change without notice and ralink assumes no responsibility for any inaccuracies tha t nay be cont ained in this document. ralink reserves the right to make change in the products to improve function, performance, reliability, and to attempt to supply the best product possible. free datasheet http://www.datasheetlist.com/

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